1b6355c895
For historical reasons, the ExecContext interface had a single function, readMem(), that did two different things depending on whether the ExecContext supported atomic memory mode (i.e., AtomicSimpleCPU) or timing memory mode (all the other models). In the former case, it actually performed a memory read; in the latter case, it merely initiated a read access, and the read completion did not happen until later when a response packet arrived from the memory system. This led to some confusing things, including timing accesses being required to provide a pointer for the return data even though that pointer was only used in atomic mode. This patch splits this interface, adding a new initiateMemRead() function to the ExecContext interface to replace the timing-mode use of readMem(). For consistency and clarity, the readMemTiming() helper function in the ISA definitions is renamed to initiateMemRead() as well. For x86, where the access size is passed in explicitly, we can also get rid of the data parameter at this level. For other ISAs, where the access size is determined from the type of the data parameter, we have to keep the parameter for that purpose.
1001 lines
29 KiB
C++
1001 lines
29 KiB
C++
/*
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* Copyright 2014 Google, Inc.
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* Copyright (c) 2010-2013,2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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*/
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#include "arch/locked_mem.hh"
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#include "arch/mmapped_ipr.hh"
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#include "arch/utility.hh"
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#include "base/bigint.hh"
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#include "config/the_isa.hh"
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#include "cpu/simple/timing.hh"
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#include "cpu/exetrace.hh"
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#include "debug/Config.hh"
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#include "debug/Drain.hh"
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#include "debug/ExecFaulting.hh"
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#include "debug/SimpleCPU.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "params/TimingSimpleCPU.hh"
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#include "sim/faults.hh"
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#include "sim/full_system.hh"
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#include "sim/system.hh"
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#include "debug/Mwait.hh"
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using namespace std;
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using namespace TheISA;
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void
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TimingSimpleCPU::init()
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{
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BaseSimpleCPU::init();
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}
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void
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TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
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{
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pkt = _pkt;
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cpu->schedule(this, t);
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}
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TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
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: BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
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dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0),
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fetchEvent(this)
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{
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_status = Idle;
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}
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TimingSimpleCPU::~TimingSimpleCPU()
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{
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}
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DrainState
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TimingSimpleCPU::drain()
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{
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if (switchedOut())
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return DrainState::Drained;
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if (_status == Idle ||
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(_status == BaseSimpleCPU::Running && isDrained())) {
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DPRINTF(Drain, "No need to drain.\n");
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activeThreads.clear();
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return DrainState::Drained;
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} else {
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DPRINTF(Drain, "Requesting drain.\n");
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// The fetch event can become descheduled if a drain didn't
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// succeed on the first attempt. We need to reschedule it if
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// the CPU is waiting for a microcode routine to complete.
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if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled())
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schedule(fetchEvent, clockEdge());
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return DrainState::Draining;
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}
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}
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void
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TimingSimpleCPU::drainResume()
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{
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assert(!fetchEvent.scheduled());
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if (switchedOut())
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return;
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DPRINTF(SimpleCPU, "Resume\n");
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verifyMemoryMode();
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assert(!threadContexts.empty());
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_status = BaseSimpleCPU::Idle;
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for (ThreadID tid = 0; tid < numThreads; tid++) {
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if (threadInfo[tid]->thread->status() == ThreadContext::Active) {
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threadInfo[tid]->notIdleFraction = 1;
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activeThreads.push_back(tid);
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_status = BaseSimpleCPU::Running;
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// Fetch if any threads active
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if (!fetchEvent.scheduled()) {
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schedule(fetchEvent, nextCycle());
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}
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} else {
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threadInfo[tid]->notIdleFraction = 0;
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}
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}
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system->totalNumInsts = 0;
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}
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bool
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TimingSimpleCPU::tryCompleteDrain()
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{
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if (drainState() != DrainState::Draining)
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return false;
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DPRINTF(Drain, "tryCompleteDrain.\n");
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if (!isDrained())
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return false;
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DPRINTF(Drain, "CPU done draining, processing drain event\n");
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signalDrainDone();
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return true;
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}
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void
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TimingSimpleCPU::switchOut()
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{
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SimpleExecContext& t_info = *threadInfo[curThread];
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M5_VAR_USED SimpleThread* thread = t_info.thread;
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BaseSimpleCPU::switchOut();
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assert(!fetchEvent.scheduled());
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assert(_status == BaseSimpleCPU::Running || _status == Idle);
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assert(!t_info.stayAtPC);
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assert(thread->microPC() == 0);
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updateCycleCounts();
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}
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void
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TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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BaseSimpleCPU::takeOverFrom(oldCPU);
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previousCycle = curCycle();
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}
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void
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TimingSimpleCPU::verifyMemoryMode() const
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{
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if (!system->isTimingMode()) {
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fatal("The timing CPU requires the memory system to be in "
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"'timing' mode.\n");
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}
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}
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void
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TimingSimpleCPU::activateContext(ThreadID thread_num)
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{
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DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num);
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assert(thread_num < numThreads);
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threadInfo[thread_num]->notIdleFraction = 1;
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if (_status == BaseSimpleCPU::Idle)
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_status = BaseSimpleCPU::Running;
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// kick things off by initiating the fetch of the next instruction
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if (!fetchEvent.scheduled())
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schedule(fetchEvent, clockEdge(Cycles(0)));
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if (std::find(activeThreads.begin(), activeThreads.end(), thread_num)
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== activeThreads.end()) {
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activeThreads.push_back(thread_num);
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}
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}
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void
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TimingSimpleCPU::suspendContext(ThreadID thread_num)
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{
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DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
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assert(thread_num < numThreads);
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activeThreads.remove(thread_num);
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if (_status == Idle)
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return;
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assert(_status == BaseSimpleCPU::Running);
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threadInfo[thread_num]->notIdleFraction = 0;
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if (activeThreads.empty()) {
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_status = Idle;
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if (fetchEvent.scheduled()) {
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deschedule(fetchEvent);
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}
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}
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}
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bool
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TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
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{
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SimpleExecContext &t_info = *threadInfo[curThread];
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SimpleThread* thread = t_info.thread;
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RequestPtr req = pkt->req;
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// We're about the issues a locked load, so tell the monitor
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// to start caring about this address
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if (pkt->isRead() && pkt->req->isLLSC()) {
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TheISA::handleLockedRead(thread, pkt->req);
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}
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if (req->isMmappedIpr()) {
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Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);
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new IprEvent(pkt, this, clockEdge(delay));
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_status = DcacheWaitResponse;
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dcache_pkt = NULL;
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} else if (!dcachePort.sendTimingReq(pkt)) {
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_status = DcacheRetry;
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dcache_pkt = pkt;
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} else {
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_status = DcacheWaitResponse;
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// memory system takes ownership of packet
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dcache_pkt = NULL;
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}
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return dcache_pkt == NULL;
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}
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void
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TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
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bool read)
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{
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SimpleExecContext &t_info = *threadInfo[curThread];
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SimpleThread* thread = t_info.thread;
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PacketPtr pkt = buildPacket(req, read);
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pkt->dataDynamic<uint8_t>(data);
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if (req->getFlags().isSet(Request::NO_ACCESS)) {
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assert(!dcache_pkt);
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pkt->makeResponse();
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completeDataAccess(pkt);
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} else if (read) {
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handleReadPacket(pkt);
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} else {
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bool do_access = true; // flag to suppress cache access
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if (req->isLLSC()) {
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do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
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} else if (req->isCondSwap()) {
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assert(res);
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req->setExtraData(*res);
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}
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if (do_access) {
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dcache_pkt = pkt;
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handleWritePacket();
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threadSnoop(pkt, curThread);
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} else {
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_status = DcacheWaitResponse;
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completeDataAccess(pkt);
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}
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}
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}
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void
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TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2,
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RequestPtr req, uint8_t *data, bool read)
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{
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PacketPtr pkt1, pkt2;
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buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read);
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if (req->getFlags().isSet(Request::NO_ACCESS)) {
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assert(!dcache_pkt);
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pkt1->makeResponse();
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completeDataAccess(pkt1);
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} else if (read) {
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SplitFragmentSenderState * send_state =
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dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
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if (handleReadPacket(pkt1)) {
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send_state->clearFromParent();
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send_state = dynamic_cast<SplitFragmentSenderState *>(
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pkt2->senderState);
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if (handleReadPacket(pkt2)) {
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send_state->clearFromParent();
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}
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}
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} else {
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dcache_pkt = pkt1;
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SplitFragmentSenderState * send_state =
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dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
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if (handleWritePacket()) {
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send_state->clearFromParent();
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dcache_pkt = pkt2;
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send_state = dynamic_cast<SplitFragmentSenderState *>(
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pkt2->senderState);
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if (handleWritePacket()) {
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send_state->clearFromParent();
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}
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}
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}
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}
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void
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TimingSimpleCPU::translationFault(const Fault &fault)
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{
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// fault may be NoFault in cases where a fault is suppressed,
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// for instance prefetches.
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updateCycleCounts();
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if (traceData) {
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// Since there was a fault, we shouldn't trace this instruction.
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delete traceData;
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traceData = NULL;
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}
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postExecute();
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advanceInst(fault);
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}
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PacketPtr
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TimingSimpleCPU::buildPacket(RequestPtr req, bool read)
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{
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return read ? Packet::createRead(req) : Packet::createWrite(req);
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}
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void
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TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
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RequestPtr req1, RequestPtr req2, RequestPtr req,
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uint8_t *data, bool read)
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{
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pkt1 = pkt2 = NULL;
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assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
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if (req->getFlags().isSet(Request::NO_ACCESS)) {
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pkt1 = buildPacket(req, read);
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return;
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}
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pkt1 = buildPacket(req1, read);
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pkt2 = buildPacket(req2, read);
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PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand());
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pkt->dataDynamic<uint8_t>(data);
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pkt1->dataStatic<uint8_t>(data);
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pkt2->dataStatic<uint8_t>(data + req1->getSize());
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SplitMainSenderState * main_send_state = new SplitMainSenderState;
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pkt->senderState = main_send_state;
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main_send_state->fragments[0] = pkt1;
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main_send_state->fragments[1] = pkt2;
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main_send_state->outstanding = 2;
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pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
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pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
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}
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Fault
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TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
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unsigned size, unsigned flags)
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{
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panic("readMem() is for atomic accesses, and should "
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"never be called on TimingSimpleCPU.\n");
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}
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Fault
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TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags)
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{
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SimpleExecContext &t_info = *threadInfo[curThread];
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SimpleThread* thread = t_info.thread;
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Fault fault;
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const int asid = 0;
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const ThreadID tid = curThread;
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const Addr pc = thread->instAddr();
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unsigned block_size = cacheLineSize();
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BaseTLB::Mode mode = BaseTLB::Read;
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if (traceData)
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traceData->setMem(addr, size, flags);
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RequestPtr req = new Request(asid, addr, size,
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flags, dataMasterId(), pc,
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thread->contextId(), tid);
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req->taskId(taskId());
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Addr split_addr = roundDown(addr + size - 1, block_size);
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assert(split_addr <= addr || split_addr - addr < block_size);
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_status = DTBWaitResponse;
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if (split_addr > addr) {
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RequestPtr req1, req2;
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assert(!req->isLLSC() && !req->isSwap());
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req->splitOnVaddr(split_addr, req1, req2);
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WholeTranslationState *state =
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new WholeTranslationState(req, req1, req2, new uint8_t[size],
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NULL, mode);
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DataTranslation<TimingSimpleCPU *> *trans1 =
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new DataTranslation<TimingSimpleCPU *>(this, state, 0);
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DataTranslation<TimingSimpleCPU *> *trans2 =
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new DataTranslation<TimingSimpleCPU *>(this, state, 1);
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thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode);
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thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode);
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} else {
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WholeTranslationState *state =
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new WholeTranslationState(req, new uint8_t[size], NULL, mode);
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DataTranslation<TimingSimpleCPU *> *translation
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= new DataTranslation<TimingSimpleCPU *>(this, state);
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thread->dtb->translateTiming(req, thread->getTC(), translation, mode);
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}
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return NoFault;
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}
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bool
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TimingSimpleCPU::handleWritePacket()
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{
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SimpleExecContext &t_info = *threadInfo[curThread];
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SimpleThread* thread = t_info.thread;
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RequestPtr req = dcache_pkt->req;
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if (req->isMmappedIpr()) {
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Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
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new IprEvent(dcache_pkt, this, clockEdge(delay));
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_status = DcacheWaitResponse;
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dcache_pkt = NULL;
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} else if (!dcachePort.sendTimingReq(dcache_pkt)) {
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_status = DcacheRetry;
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} else {
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_status = DcacheWaitResponse;
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// memory system takes ownership of packet
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dcache_pkt = NULL;
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}
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return dcache_pkt == NULL;
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}
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Fault
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TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
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Addr addr, unsigned flags, uint64_t *res)
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{
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SimpleExecContext &t_info = *threadInfo[curThread];
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SimpleThread* thread = t_info.thread;
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uint8_t *newData = new uint8_t[size];
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const int asid = 0;
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const ThreadID tid = curThread;
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const Addr pc = thread->instAddr();
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unsigned block_size = cacheLineSize();
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BaseTLB::Mode mode = BaseTLB::Write;
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if (data == NULL) {
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assert(flags & Request::CACHE_BLOCK_ZERO);
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// This must be a cache block cleaning request
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memset(newData, 0, size);
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} else {
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memcpy(newData, data, size);
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}
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if (traceData)
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traceData->setMem(addr, size, flags);
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RequestPtr req = new Request(asid, addr, size,
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flags, dataMasterId(), pc,
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thread->contextId(), tid);
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req->taskId(taskId());
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Addr split_addr = roundDown(addr + size - 1, block_size);
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assert(split_addr <= addr || split_addr - addr < block_size);
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_status = DTBWaitResponse;
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if (split_addr > addr) {
|
|
RequestPtr req1, req2;
|
|
assert(!req->isLLSC() && !req->isSwap());
|
|
req->splitOnVaddr(split_addr, req1, req2);
|
|
|
|
WholeTranslationState *state =
|
|
new WholeTranslationState(req, req1, req2, newData, res, mode);
|
|
DataTranslation<TimingSimpleCPU *> *trans1 =
|
|
new DataTranslation<TimingSimpleCPU *>(this, state, 0);
|
|
DataTranslation<TimingSimpleCPU *> *trans2 =
|
|
new DataTranslation<TimingSimpleCPU *>(this, state, 1);
|
|
|
|
thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode);
|
|
thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode);
|
|
} else {
|
|
WholeTranslationState *state =
|
|
new WholeTranslationState(req, newData, res, mode);
|
|
DataTranslation<TimingSimpleCPU *> *translation =
|
|
new DataTranslation<TimingSimpleCPU *>(this, state);
|
|
thread->dtb->translateTiming(req, thread->getTC(), translation, mode);
|
|
}
|
|
|
|
// Translation faults will be returned via finishTranslation()
|
|
return NoFault;
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
|
|
{
|
|
for (ThreadID tid = 0; tid < numThreads; tid++) {
|
|
if (tid != sender) {
|
|
if(getCpuAddrMonitor(tid)->doMonitor(pkt)) {
|
|
wakeup(tid);
|
|
}
|
|
TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt,
|
|
dcachePort.cacheBlockMask);
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
|
|
{
|
|
_status = BaseSimpleCPU::Running;
|
|
|
|
if (state->getFault() != NoFault) {
|
|
if (state->isPrefetch()) {
|
|
state->setNoFault();
|
|
}
|
|
delete [] state->data;
|
|
state->deleteReqs();
|
|
translationFault(state->getFault());
|
|
} else {
|
|
if (!state->isSplit) {
|
|
sendData(state->mainReq, state->data, state->res,
|
|
state->mode == BaseTLB::Read);
|
|
} else {
|
|
sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq,
|
|
state->data, state->mode == BaseTLB::Read);
|
|
}
|
|
}
|
|
|
|
delete state;
|
|
}
|
|
|
|
|
|
void
|
|
TimingSimpleCPU::fetch()
|
|
{
|
|
// Change thread if multi-threaded
|
|
swapActiveThread();
|
|
|
|
SimpleExecContext &t_info = *threadInfo[curThread];
|
|
SimpleThread* thread = t_info.thread;
|
|
|
|
DPRINTF(SimpleCPU, "Fetch\n");
|
|
|
|
if (!curStaticInst || !curStaticInst->isDelayedCommit()) {
|
|
checkForInterrupts();
|
|
checkPcEventQueue();
|
|
}
|
|
|
|
// We must have just got suspended by a PC event
|
|
if (_status == Idle)
|
|
return;
|
|
|
|
TheISA::PCState pcState = thread->pcState();
|
|
bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
|
|
!curMacroStaticInst;
|
|
|
|
if (needToFetch) {
|
|
_status = BaseSimpleCPU::Running;
|
|
Request *ifetch_req = new Request();
|
|
ifetch_req->taskId(taskId());
|
|
ifetch_req->setThreadContext(thread->contextId(), curThread);
|
|
setupFetchRequest(ifetch_req);
|
|
DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
|
|
thread->itb->translateTiming(ifetch_req, thread->getTC(),
|
|
&fetchTranslation, BaseTLB::Execute);
|
|
} else {
|
|
_status = IcacheWaitResponse;
|
|
completeIfetch(NULL);
|
|
|
|
updateCycleCounts();
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req,
|
|
ThreadContext *tc)
|
|
{
|
|
if (fault == NoFault) {
|
|
DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
|
|
req->getVaddr(), req->getPaddr());
|
|
ifetch_pkt = new Packet(req, MemCmd::ReadReq);
|
|
ifetch_pkt->dataStatic(&inst);
|
|
DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
|
|
|
|
if (!icachePort.sendTimingReq(ifetch_pkt)) {
|
|
// Need to wait for retry
|
|
_status = IcacheRetry;
|
|
} else {
|
|
// Need to wait for cache to respond
|
|
_status = IcacheWaitResponse;
|
|
// ownership of packet transferred to memory system
|
|
ifetch_pkt = NULL;
|
|
}
|
|
} else {
|
|
DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr());
|
|
delete req;
|
|
// fetch fault: advance directly to next instruction (fault handler)
|
|
_status = BaseSimpleCPU::Running;
|
|
advanceInst(fault);
|
|
}
|
|
|
|
updateCycleCounts();
|
|
}
|
|
|
|
|
|
void
|
|
TimingSimpleCPU::advanceInst(const Fault &fault)
|
|
{
|
|
SimpleExecContext &t_info = *threadInfo[curThread];
|
|
|
|
if (_status == Faulting)
|
|
return;
|
|
|
|
if (fault != NoFault) {
|
|
advancePC(fault);
|
|
DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
|
|
reschedule(fetchEvent, clockEdge(), true);
|
|
_status = Faulting;
|
|
return;
|
|
}
|
|
|
|
|
|
if (!t_info.stayAtPC)
|
|
advancePC(fault);
|
|
|
|
if (tryCompleteDrain())
|
|
return;
|
|
|
|
if (_status == BaseSimpleCPU::Running) {
|
|
// kick off fetch of next instruction... callback from icache
|
|
// response will cause that instruction to be executed,
|
|
// keeping the CPU running.
|
|
fetch();
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
TimingSimpleCPU::completeIfetch(PacketPtr pkt)
|
|
{
|
|
SimpleExecContext& t_info = *threadInfo[curThread];
|
|
|
|
DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ?
|
|
pkt->getAddr() : 0);
|
|
|
|
// received a response from the icache: execute the received
|
|
// instruction
|
|
assert(!pkt || !pkt->isError());
|
|
assert(_status == IcacheWaitResponse);
|
|
|
|
_status = BaseSimpleCPU::Running;
|
|
|
|
updateCycleCounts();
|
|
|
|
if (pkt)
|
|
pkt->req->setAccessLatency();
|
|
|
|
|
|
preExecute();
|
|
if (curStaticInst && curStaticInst->isMemRef()) {
|
|
// load or store: just send to dcache
|
|
Fault fault = curStaticInst->initiateAcc(&t_info, traceData);
|
|
|
|
// If we're not running now the instruction will complete in a dcache
|
|
// response callback or the instruction faulted and has started an
|
|
// ifetch
|
|
if (_status == BaseSimpleCPU::Running) {
|
|
if (fault != NoFault && traceData) {
|
|
// If there was a fault, we shouldn't trace this instruction.
|
|
delete traceData;
|
|
traceData = NULL;
|
|
}
|
|
|
|
postExecute();
|
|
// @todo remove me after debugging with legion done
|
|
if (curStaticInst && (!curStaticInst->isMicroop() ||
|
|
curStaticInst->isFirstMicroop()))
|
|
instCnt++;
|
|
advanceInst(fault);
|
|
}
|
|
} else if (curStaticInst) {
|
|
// non-memory instruction: execute completely now
|
|
Fault fault = curStaticInst->execute(&t_info, traceData);
|
|
|
|
// keep an instruction count
|
|
if (fault == NoFault)
|
|
countInst();
|
|
else if (traceData && !DTRACE(ExecFaulting)) {
|
|
delete traceData;
|
|
traceData = NULL;
|
|
}
|
|
|
|
postExecute();
|
|
// @todo remove me after debugging with legion done
|
|
if (curStaticInst && (!curStaticInst->isMicroop() ||
|
|
curStaticInst->isFirstMicroop()))
|
|
instCnt++;
|
|
advanceInst(fault);
|
|
} else {
|
|
advanceInst(NoFault);
|
|
}
|
|
|
|
if (pkt) {
|
|
delete pkt->req;
|
|
delete pkt;
|
|
}
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::IcachePort::ITickEvent::process()
|
|
{
|
|
cpu->completeIfetch(pkt);
|
|
}
|
|
|
|
bool
|
|
TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
|
|
{
|
|
DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr());
|
|
// we should only ever see one response per cycle since we only
|
|
// issue a new request once this response is sunk
|
|
assert(!tickEvent.scheduled());
|
|
// delay processing of returned data until next CPU clock edge
|
|
tickEvent.schedule(pkt, cpu->clockEdge());
|
|
|
|
return true;
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::IcachePort::recvReqRetry()
|
|
{
|
|
// we shouldn't get a retry unless we have a packet that we're
|
|
// waiting to transmit
|
|
assert(cpu->ifetch_pkt != NULL);
|
|
assert(cpu->_status == IcacheRetry);
|
|
PacketPtr tmp = cpu->ifetch_pkt;
|
|
if (sendTimingReq(tmp)) {
|
|
cpu->_status = IcacheWaitResponse;
|
|
cpu->ifetch_pkt = NULL;
|
|
}
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
|
|
{
|
|
// received a response from the dcache: complete the load or store
|
|
// instruction
|
|
assert(!pkt->isError());
|
|
assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
|
|
pkt->req->getFlags().isSet(Request::NO_ACCESS));
|
|
|
|
pkt->req->setAccessLatency();
|
|
|
|
updateCycleCounts();
|
|
|
|
if (pkt->senderState) {
|
|
SplitFragmentSenderState * send_state =
|
|
dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
|
|
assert(send_state);
|
|
delete pkt->req;
|
|
delete pkt;
|
|
PacketPtr big_pkt = send_state->bigPkt;
|
|
delete send_state;
|
|
|
|
SplitMainSenderState * main_send_state =
|
|
dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
|
|
assert(main_send_state);
|
|
// Record the fact that this packet is no longer outstanding.
|
|
assert(main_send_state->outstanding != 0);
|
|
main_send_state->outstanding--;
|
|
|
|
if (main_send_state->outstanding) {
|
|
return;
|
|
} else {
|
|
delete main_send_state;
|
|
big_pkt->senderState = NULL;
|
|
pkt = big_pkt;
|
|
}
|
|
}
|
|
|
|
_status = BaseSimpleCPU::Running;
|
|
|
|
Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread],
|
|
traceData);
|
|
|
|
// keep an instruction count
|
|
if (fault == NoFault)
|
|
countInst();
|
|
else if (traceData) {
|
|
// If there was a fault, we shouldn't trace this instruction.
|
|
delete traceData;
|
|
traceData = NULL;
|
|
}
|
|
|
|
delete pkt->req;
|
|
delete pkt;
|
|
|
|
postExecute();
|
|
|
|
advanceInst(fault);
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::updateCycleCounts()
|
|
{
|
|
const Cycles delta(curCycle() - previousCycle);
|
|
|
|
numCycles += delta;
|
|
ppCycles->notify(delta);
|
|
|
|
previousCycle = curCycle();
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
|
|
{
|
|
for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
|
|
if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
|
|
cpu->wakeup(tid);
|
|
}
|
|
}
|
|
|
|
for (auto &t_info : cpu->threadInfo) {
|
|
TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
|
|
}
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt)
|
|
{
|
|
for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
|
|
if(cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
|
|
cpu->wakeup(tid);
|
|
}
|
|
}
|
|
}
|
|
|
|
bool
|
|
TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
|
|
{
|
|
DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr());
|
|
|
|
// The timing CPU is not really ticked, instead it relies on the
|
|
// memory system (fetch and load/store) to set the pace.
|
|
if (!tickEvent.scheduled()) {
|
|
// Delay processing of returned data until next CPU clock edge
|
|
tickEvent.schedule(pkt, cpu->clockEdge());
|
|
return true;
|
|
} else {
|
|
// In the case of a split transaction and a cache that is
|
|
// faster than a CPU we could get two responses in the
|
|
// same tick, delay the second one
|
|
if (!retryRespEvent.scheduled())
|
|
cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1)));
|
|
return false;
|
|
}
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::DcachePort::DTickEvent::process()
|
|
{
|
|
cpu->completeDataAccess(pkt);
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::DcachePort::recvReqRetry()
|
|
{
|
|
// we shouldn't get a retry unless we have a packet that we're
|
|
// waiting to transmit
|
|
assert(cpu->dcache_pkt != NULL);
|
|
assert(cpu->_status == DcacheRetry);
|
|
PacketPtr tmp = cpu->dcache_pkt;
|
|
if (tmp->senderState) {
|
|
// This is a packet from a split access.
|
|
SplitFragmentSenderState * send_state =
|
|
dynamic_cast<SplitFragmentSenderState *>(tmp->senderState);
|
|
assert(send_state);
|
|
PacketPtr big_pkt = send_state->bigPkt;
|
|
|
|
SplitMainSenderState * main_send_state =
|
|
dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
|
|
assert(main_send_state);
|
|
|
|
if (sendTimingReq(tmp)) {
|
|
// If we were able to send without retrying, record that fact
|
|
// and try sending the other fragment.
|
|
send_state->clearFromParent();
|
|
int other_index = main_send_state->getPendingFragment();
|
|
if (other_index > 0) {
|
|
tmp = main_send_state->fragments[other_index];
|
|
cpu->dcache_pkt = tmp;
|
|
if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) ||
|
|
(big_pkt->isWrite() && cpu->handleWritePacket())) {
|
|
main_send_state->fragments[other_index] = NULL;
|
|
}
|
|
} else {
|
|
cpu->_status = DcacheWaitResponse;
|
|
// memory system takes ownership of packet
|
|
cpu->dcache_pkt = NULL;
|
|
}
|
|
}
|
|
} else if (sendTimingReq(tmp)) {
|
|
cpu->_status = DcacheWaitResponse;
|
|
// memory system takes ownership of packet
|
|
cpu->dcache_pkt = NULL;
|
|
}
|
|
}
|
|
|
|
TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu,
|
|
Tick t)
|
|
: pkt(_pkt), cpu(_cpu)
|
|
{
|
|
cpu->schedule(this, t);
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::IprEvent::process()
|
|
{
|
|
cpu->completeDataAccess(pkt);
|
|
}
|
|
|
|
const char *
|
|
TimingSimpleCPU::IprEvent::description() const
|
|
{
|
|
return "Timing Simple CPU Delay IPR event";
|
|
}
|
|
|
|
|
|
void
|
|
TimingSimpleCPU::printAddr(Addr a)
|
|
{
|
|
dcachePort.printAddr(a);
|
|
}
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// TimingSimpleCPU Simulation Object
|
|
//
|
|
TimingSimpleCPU *
|
|
TimingSimpleCPUParams::create()
|
|
{
|
|
return new TimingSimpleCPU(this);
|
|
}
|