1347 lines
151 KiB
Plaintext
1347 lines
151 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000729 # Number of seconds simulated
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sim_ticks 729071000 # Number of ticks simulated
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final_tick 729071000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1157540 # Simulator instruction rate (inst/s)
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host_op_rate 1157526 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 421963637 # Simulator tick rate (ticks/s)
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host_mem_usage 274580 # Number of bytes of host memory used
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host_seconds 1.73 # Real time elapsed on the host
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sim_insts 1999959 # Number of instructions simulated
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sim_ops 1999959 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 29056 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 25792 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 29056 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.inst 25792 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.data 29056 # Number of bytes read from this memory
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system.physmem.bytes_read::total 219392 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 25792 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 25792 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 25792 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu3.inst 25792 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 103168 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu0.inst 403 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 454 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 403 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 454 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 403 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 454 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 35376527 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 39853457 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 35376527 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 39853457 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 35376527 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 39853457 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.inst 35376527 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.data 39853457 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 300919938 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 35376527 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 35376527 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 35376527 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu3.inst 35376527 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 141506108 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 35376527 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 39853457 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 35376527 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 39853457 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 35376527 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 39853457 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.inst 35376527 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.data 39853457 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 300919938 # Total bandwidth to/from this memory (bytes/s)
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system.cpu0.dtb.fetch_hits 0 # ITB hits
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system.cpu0.dtb.fetch_misses 0 # ITB misses
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system.cpu0.dtb.fetch_acv 0 # ITB acv
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system.cpu0.dtb.fetch_accesses 0 # ITB accesses
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system.cpu0.dtb.read_hits 124435 # DTB read hits
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system.cpu0.dtb.read_misses 8 # DTB read misses
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system.cpu0.dtb.read_acv 0 # DTB read access violations
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system.cpu0.dtb.read_accesses 124443 # DTB read accesses
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system.cpu0.dtb.write_hits 56340 # DTB write hits
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system.cpu0.dtb.write_misses 10 # DTB write misses
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system.cpu0.dtb.write_acv 0 # DTB write access violations
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system.cpu0.dtb.write_accesses 56350 # DTB write accesses
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system.cpu0.dtb.data_hits 180775 # DTB hits
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system.cpu0.dtb.data_misses 18 # DTB misses
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system.cpu0.dtb.data_acv 0 # DTB access violations
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system.cpu0.dtb.data_accesses 180793 # DTB accesses
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system.cpu0.itb.fetch_hits 500020 # ITB hits
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system.cpu0.itb.fetch_misses 13 # ITB misses
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system.cpu0.itb.fetch_acv 0 # ITB acv
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system.cpu0.itb.fetch_accesses 500033 # ITB accesses
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system.cpu0.itb.read_hits 0 # DTB read hits
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system.cpu0.itb.read_misses 0 # DTB read misses
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system.cpu0.itb.read_acv 0 # DTB read access violations
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system.cpu0.itb.read_accesses 0 # DTB read accesses
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system.cpu0.itb.write_hits 0 # DTB write hits
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system.cpu0.itb.write_misses 0 # DTB write misses
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system.cpu0.itb.write_acv 0 # DTB write access violations
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system.cpu0.itb.write_accesses 0 # DTB write accesses
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system.cpu0.itb.data_hits 0 # DTB hits
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system.cpu0.itb.data_misses 0 # DTB misses
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system.cpu0.itb.data_acv 0 # DTB access violations
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system.cpu0.itb.data_accesses 0 # DTB accesses
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system.cpu0.workload.num_syscalls 18 # Number of system calls
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system.cpu0.numCycles 1458142 # number of cpu cycles simulated
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu0.committedInsts 500001 # Number of instructions committed
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system.cpu0.committedOps 500001 # Number of ops (including micro ops) committed
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system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses
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system.cpu0.num_fp_alu_accesses 32 # Number of float alu accesses
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system.cpu0.num_func_calls 14357 # number of times a function call or return occured
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system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls
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system.cpu0.num_int_insts 474689 # number of integer instructions
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system.cpu0.num_fp_insts 32 # number of float instructions
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system.cpu0.num_int_register_reads 654286 # number of times the integer registers were read
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system.cpu0.num_int_register_writes 371542 # number of times the integer registers were written
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system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read
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system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written
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system.cpu0.num_mem_refs 180793 # number of memory refs
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system.cpu0.num_load_insts 124443 # Number of load instructions
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system.cpu0.num_store_insts 56350 # Number of store instructions
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system.cpu0.num_idle_cycles 0 # Number of idle cycles
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system.cpu0.num_busy_cycles 1458142 # Number of busy cycles
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system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu0.idle_fraction 0 # Percentage of idle cycles
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system.cpu0.icache.replacements 152 # number of replacements
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system.cpu0.icache.tagsinuse 216.378486 # Cycle average of tags in use
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system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks.
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system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
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system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks.
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system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.icache.occ_blocks::cpu0.inst 216.378486 # Average occupied blocks per requestor
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system.cpu0.icache.occ_percent::cpu0.inst 0.422614 # Average percentage of cache occupancy
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system.cpu0.icache.occ_percent::total 0.422614 # Average percentage of cache occupancy
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system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits
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system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits
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system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits
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system.cpu0.icache.demand_hits::total 499557 # number of demand (read+write) hits
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system.cpu0.icache.overall_hits::cpu0.inst 499557 # number of overall hits
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system.cpu0.icache.overall_hits::total 499557 # number of overall hits
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system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses
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system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses
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system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses
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system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
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system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
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system.cpu0.icache.overall_misses::total 463 # number of overall misses
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system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 23142000 # number of ReadReq miss cycles
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system.cpu0.icache.ReadReq_miss_latency::total 23142000 # number of ReadReq miss cycles
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system.cpu0.icache.demand_miss_latency::cpu0.inst 23142000 # number of demand (read+write) miss cycles
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system.cpu0.icache.demand_miss_latency::total 23142000 # number of demand (read+write) miss cycles
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system.cpu0.icache.overall_miss_latency::cpu0.inst 23142000 # number of overall miss cycles
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system.cpu0.icache.overall_miss_latency::total 23142000 # number of overall miss cycles
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system.cpu0.icache.ReadReq_accesses::cpu0.inst 500020 # number of ReadReq accesses(hits+misses)
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system.cpu0.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
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system.cpu0.icache.demand_accesses::cpu0.inst 500020 # number of demand (read+write) accesses
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system.cpu0.icache.demand_accesses::total 500020 # number of demand (read+write) accesses
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system.cpu0.icache.overall_accesses::cpu0.inst 500020 # number of overall (read+write) accesses
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system.cpu0.icache.overall_accesses::total 500020 # number of overall (read+write) accesses
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system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
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system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
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system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
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system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
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system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
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system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
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system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 49982.721382 # average ReadReq miss latency
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system.cpu0.icache.ReadReq_avg_miss_latency::total 49982.721382 # average ReadReq miss latency
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system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 49982.721382 # average overall miss latency
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system.cpu0.icache.demand_avg_miss_latency::total 49982.721382 # average overall miss latency
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system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 49982.721382 # average overall miss latency
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system.cpu0.icache.overall_avg_miss_latency::total 49982.721382 # average overall miss latency
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system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.icache.fast_writes 0 # number of fast writes performed
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system.cpu0.icache.cache_copies 0 # number of cache copies performed
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system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 463 # number of ReadReq MSHR misses
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system.cpu0.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
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system.cpu0.icache.demand_mshr_misses::cpu0.inst 463 # number of demand (read+write) MSHR misses
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system.cpu0.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
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system.cpu0.icache.overall_mshr_misses::cpu0.inst 463 # number of overall MSHR misses
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system.cpu0.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
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system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22216000 # number of ReadReq MSHR miss cycles
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system.cpu0.icache.ReadReq_mshr_miss_latency::total 22216000 # number of ReadReq MSHR miss cycles
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system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22216000 # number of demand (read+write) MSHR miss cycles
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system.cpu0.icache.demand_mshr_miss_latency::total 22216000 # number of demand (read+write) MSHR miss cycles
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system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22216000 # number of overall MSHR miss cycles
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system.cpu0.icache.overall_mshr_miss_latency::total 22216000 # number of overall MSHR miss cycles
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system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses
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system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
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system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses
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system.cpu0.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
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system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for overall accesses
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system.cpu0.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
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system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47982.721382 # average ReadReq mshr miss latency
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system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47982.721382 # average ReadReq mshr miss latency
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system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47982.721382 # average overall mshr miss latency
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system.cpu0.icache.demand_avg_mshr_miss_latency::total 47982.721382 # average overall mshr miss latency
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system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47982.721382 # average overall mshr miss latency
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system.cpu0.icache.overall_avg_mshr_miss_latency::total 47982.721382 # average overall mshr miss latency
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.replacements 61 # number of replacements
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|
system.cpu0.dcache.tagsinuse 273.500836 # Cycle average of tags in use
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|
system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
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|
system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
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|
system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
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|
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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|
system.cpu0.dcache.occ_blocks::cpu0.data 273.500836 # Average occupied blocks per requestor
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|
system.cpu0.dcache.occ_percent::cpu0.data 0.534181 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.occ_percent::total 0.534181 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
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|
system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
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|
system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 180312 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 180312 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 180312 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 180312 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 324 # number of ReadReq misses
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|
system.cpu0.dcache.ReadReq_misses::total 324 # number of ReadReq misses
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|
system.cpu0.dcache.WriteReq_misses::cpu0.data 139 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 139 # number of WriteReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 463 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 463 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17475500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 17475500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7669500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 7669500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 25145000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 25145000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 25145000 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 25145000 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 180775 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53936.728395 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 53936.728395 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 55176.258993 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 55176.258993 # average WriteReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 54308.855292 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 54308.855292 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 54308.855292 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 54308.855292 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 29 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 324 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 139 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 463 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 463 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 16827500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 16827500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7391500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7391500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24219000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 24219000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24219000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 24219000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002604 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002467 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 51936.728395 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 51936.728395 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 53176.258993 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 53176.258993 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 52308.855292 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 52308.855292 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 52308.855292 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 52308.855292 # average overall mshr miss latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu1.dtb.read_hits 124435 # DTB read hits
|
|
system.cpu1.dtb.read_misses 8 # DTB read misses
|
|
system.cpu1.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu1.dtb.read_accesses 124443 # DTB read accesses
|
|
system.cpu1.dtb.write_hits 56339 # DTB write hits
|
|
system.cpu1.dtb.write_misses 10 # DTB write misses
|
|
system.cpu1.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu1.dtb.write_accesses 56349 # DTB write accesses
|
|
system.cpu1.dtb.data_hits 180774 # DTB hits
|
|
system.cpu1.dtb.data_misses 18 # DTB misses
|
|
system.cpu1.dtb.data_acv 0 # DTB access violations
|
|
system.cpu1.dtb.data_accesses 180792 # DTB accesses
|
|
system.cpu1.itb.fetch_hits 500012 # ITB hits
|
|
system.cpu1.itb.fetch_misses 13 # ITB misses
|
|
system.cpu1.itb.fetch_acv 0 # ITB acv
|
|
system.cpu1.itb.fetch_accesses 500025 # ITB accesses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.read_acv 0 # DTB read access violations
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.write_acv 0 # DTB write access violations
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.data_hits 0 # DTB hits
|
|
system.cpu1.itb.data_misses 0 # DTB misses
|
|
system.cpu1.itb.data_acv 0 # DTB access violations
|
|
system.cpu1.itb.data_accesses 0 # DTB accesses
|
|
system.cpu1.workload.num_syscalls 18 # Number of system calls
|
|
system.cpu1.numCycles 1458142 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 499993 # Number of instructions committed
|
|
system.cpu1.committedOps 499993 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 474681 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 14357 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 38179 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 474681 # number of integer instructions
|
|
system.cpu1.num_fp_insts 32 # number of float instructions
|
|
system.cpu1.num_int_register_reads 654273 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 371536 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 180792 # number of memory refs
|
|
system.cpu1.num_load_insts 124443 # Number of load instructions
|
|
system.cpu1.num_store_insts 56349 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 0 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 1458142 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0 # Percentage of idle cycles
|
|
system.cpu1.icache.replacements 152 # number of replacements
|
|
system.cpu1.icache.tagsinuse 216.374608 # Cycle average of tags in use
|
|
system.cpu1.icache.total_refs 499549 # Total number of references to valid blocks.
|
|
system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.avg_refs 1078.939525 # Average number of references to valid blocks.
|
|
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.occ_blocks::cpu1.inst 216.374608 # Average occupied blocks per requestor
|
|
system.cpu1.icache.occ_percent::cpu1.inst 0.422607 # Average percentage of cache occupancy
|
|
system.cpu1.icache.occ_percent::total 0.422607 # Average percentage of cache occupancy
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 499549 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 499549 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 499549 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 499549 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 499549 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 499549 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 463 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 463 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 463 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 463 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 23145500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 23145500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 23145500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 23145500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 23145500 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 23145500 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 500012 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 500012 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 500012 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 500012 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 500012 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 500012 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 49990.280778 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 49990.280778 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 49990.280778 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 49990.280778 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 49990.280778 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 49990.280778 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 463 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 463 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 22219500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 22219500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 22219500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 22219500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 22219500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 22219500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 47990.280778 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 47990.280778 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 47990.280778 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 47990.280778 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47990.280778 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 47990.280778 # average overall mshr miss latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.replacements 61 # number of replacements
|
|
system.cpu1.dcache.tagsinuse 273.495853 # Cycle average of tags in use
|
|
system.cpu1.dcache.total_refs 180311 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.avg_refs 389.440605 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.occ_blocks::cpu1.data 273.495853 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.occ_percent::cpu1.data 0.534172 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.occ_percent::total 0.534172 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 56200 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 180311 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 180311 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 180311 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 180311 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 324 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 324 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 463 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 463 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 17480000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 17480000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7670500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 7670500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 25150500 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 25150500 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 25150500 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 25150500 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 56339 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 180774 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 180774 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 180774 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 180774 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 53950.617284 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 53950.617284 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 55183.453237 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 55183.453237 # average WriteReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 54320.734341 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 54320.734341 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 54320.734341 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 54320.734341 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 29 # number of writebacks
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 324 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 139 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 463 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 463 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 16832000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 16832000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7392500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7392500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 24224500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 24224500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 24224500 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 24224500 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002604 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002467 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 51950.617284 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 51950.617284 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 53183.453237 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 53183.453237 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 52320.734341 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 52320.734341 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 52320.734341 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 52320.734341 # average overall mshr miss latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu2.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu2.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu2.dtb.read_hits 124433 # DTB read hits
|
|
system.cpu2.dtb.read_misses 8 # DTB read misses
|
|
system.cpu2.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu2.dtb.read_accesses 124441 # DTB read accesses
|
|
system.cpu2.dtb.write_hits 56339 # DTB write hits
|
|
system.cpu2.dtb.write_misses 10 # DTB write misses
|
|
system.cpu2.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu2.dtb.write_accesses 56349 # DTB write accesses
|
|
system.cpu2.dtb.data_hits 180772 # DTB hits
|
|
system.cpu2.dtb.data_misses 18 # DTB misses
|
|
system.cpu2.dtb.data_acv 0 # DTB access violations
|
|
system.cpu2.dtb.data_accesses 180790 # DTB accesses
|
|
system.cpu2.itb.fetch_hits 500005 # ITB hits
|
|
system.cpu2.itb.fetch_misses 13 # ITB misses
|
|
system.cpu2.itb.fetch_acv 0 # ITB acv
|
|
system.cpu2.itb.fetch_accesses 500018 # ITB accesses
|
|
system.cpu2.itb.read_hits 0 # DTB read hits
|
|
system.cpu2.itb.read_misses 0 # DTB read misses
|
|
system.cpu2.itb.read_acv 0 # DTB read access violations
|
|
system.cpu2.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.itb.write_hits 0 # DTB write hits
|
|
system.cpu2.itb.write_misses 0 # DTB write misses
|
|
system.cpu2.itb.write_acv 0 # DTB write access violations
|
|
system.cpu2.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.itb.data_hits 0 # DTB hits
|
|
system.cpu2.itb.data_misses 0 # DTB misses
|
|
system.cpu2.itb.data_acv 0 # DTB access violations
|
|
system.cpu2.itb.data_accesses 0 # DTB accesses
|
|
system.cpu2.workload.num_syscalls 18 # Number of system calls
|
|
system.cpu2.numCycles 1458142 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.committedInsts 499986 # Number of instructions committed
|
|
system.cpu2.committedOps 499986 # Number of ops (including micro ops) committed
|
|
system.cpu2.num_int_alu_accesses 474674 # Number of integer alu accesses
|
|
system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses
|
|
system.cpu2.num_func_calls 14357 # number of times a function call or return occured
|
|
system.cpu2.num_conditional_control_insts 38179 # number of instructions that are conditional controls
|
|
system.cpu2.num_int_insts 474674 # number of integer instructions
|
|
system.cpu2.num_fp_insts 32 # number of float instructions
|
|
system.cpu2.num_int_register_reads 654263 # number of times the integer registers were read
|
|
system.cpu2.num_int_register_writes 371529 # number of times the integer registers were written
|
|
system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read
|
|
system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written
|
|
system.cpu2.num_mem_refs 180790 # number of memory refs
|
|
system.cpu2.num_load_insts 124441 # Number of load instructions
|
|
system.cpu2.num_store_insts 56349 # Number of store instructions
|
|
system.cpu2.num_idle_cycles 0 # Number of idle cycles
|
|
system.cpu2.num_busy_cycles 1458142 # Number of busy cycles
|
|
system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
system.cpu2.idle_fraction 0 # Percentage of idle cycles
|
|
system.cpu2.icache.replacements 152 # number of replacements
|
|
system.cpu2.icache.tagsinuse 216.370489 # Cycle average of tags in use
|
|
system.cpu2.icache.total_refs 499542 # Total number of references to valid blocks.
|
|
system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu2.icache.avg_refs 1078.924406 # Average number of references to valid blocks.
|
|
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.icache.occ_blocks::cpu2.inst 216.370489 # Average occupied blocks per requestor
|
|
system.cpu2.icache.occ_percent::cpu2.inst 0.422599 # Average percentage of cache occupancy
|
|
system.cpu2.icache.occ_percent::total 0.422599 # Average percentage of cache occupancy
|
|
system.cpu2.icache.ReadReq_hits::cpu2.inst 499542 # number of ReadReq hits
|
|
system.cpu2.icache.ReadReq_hits::total 499542 # number of ReadReq hits
|
|
system.cpu2.icache.demand_hits::cpu2.inst 499542 # number of demand (read+write) hits
|
|
system.cpu2.icache.demand_hits::total 499542 # number of demand (read+write) hits
|
|
system.cpu2.icache.overall_hits::cpu2.inst 499542 # number of overall hits
|
|
system.cpu2.icache.overall_hits::total 499542 # number of overall hits
|
|
system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses
|
|
system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses
|
|
system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses
|
|
system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses
|
|
system.cpu2.icache.overall_misses::total 463 # number of overall misses
|
|
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 23141000 # number of ReadReq miss cycles
|
|
system.cpu2.icache.ReadReq_miss_latency::total 23141000 # number of ReadReq miss cycles
|
|
system.cpu2.icache.demand_miss_latency::cpu2.inst 23141000 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.demand_miss_latency::total 23141000 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.overall_miss_latency::cpu2.inst 23141000 # number of overall miss cycles
|
|
system.cpu2.icache.overall_miss_latency::total 23141000 # number of overall miss cycles
|
|
system.cpu2.icache.ReadReq_accesses::cpu2.inst 500005 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.ReadReq_accesses::total 500005 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.demand_accesses::cpu2.inst 500005 # number of demand (read+write) accesses
|
|
system.cpu2.icache.demand_accesses::total 500005 # number of demand (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::cpu2.inst 500005 # number of overall (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::total 500005 # number of overall (read+write) accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses
|
|
system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
|
|
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses
|
|
system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 49980.561555 # average ReadReq miss latency
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::total 49980.561555 # average ReadReq miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 49980.561555 # average overall miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::total 49980.561555 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 49980.561555 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::total 49980.561555 # average overall miss latency
|
|
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 463 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::cpu2.inst 463 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::cpu2.inst 463 # number of overall MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 22215000 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::total 22215000 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 22215000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::total 22215000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 22215000 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::total 22215000 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 47980.561555 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 47980.561555 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 47980.561555 # average overall mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::total 47980.561555 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 47980.561555 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::total 47980.561555 # average overall mshr miss latency
|
|
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.dcache.replacements 61 # number of replacements
|
|
system.cpu2.dcache.tagsinuse 273.490811 # Cycle average of tags in use
|
|
system.cpu2.dcache.total_refs 180309 # Total number of references to valid blocks.
|
|
system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu2.dcache.avg_refs 389.436285 # Average number of references to valid blocks.
|
|
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.dcache.occ_blocks::cpu2.data 273.490811 # Average occupied blocks per requestor
|
|
system.cpu2.dcache.occ_percent::cpu2.data 0.534162 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.occ_percent::total 0.534162 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.ReadReq_hits::cpu2.data 124109 # number of ReadReq hits
|
|
system.cpu2.dcache.ReadReq_hits::total 124109 # number of ReadReq hits
|
|
system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits
|
|
system.cpu2.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
|
|
system.cpu2.dcache.demand_hits::cpu2.data 180309 # number of demand (read+write) hits
|
|
system.cpu2.dcache.demand_hits::total 180309 # number of demand (read+write) hits
|
|
system.cpu2.dcache.overall_hits::cpu2.data 180309 # number of overall hits
|
|
system.cpu2.dcache.overall_hits::total 180309 # number of overall hits
|
|
system.cpu2.dcache.ReadReq_misses::cpu2.data 324 # number of ReadReq misses
|
|
system.cpu2.dcache.ReadReq_misses::total 324 # number of ReadReq misses
|
|
system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses
|
|
system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses
|
|
system.cpu2.dcache.demand_misses::cpu2.data 463 # number of demand (read+write) misses
|
|
system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses
|
|
system.cpu2.dcache.overall_misses::total 463 # number of overall misses
|
|
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 17485000 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.ReadReq_miss_latency::total 17485000 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 7679000 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::total 7679000 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::cpu2.data 25164000 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::total 25164000 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::cpu2.data 25164000 # number of overall miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::total 25164000 # number of overall miss cycles
|
|
system.cpu2.dcache.ReadReq_accesses::cpu2.data 124433 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.ReadReq_accesses::total 124433 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::cpu2.data 56339 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.demand_accesses::cpu2.data 180772 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.demand_accesses::total 180772 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::cpu2.data 180772 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::total 180772 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 # miss rate for demand accesses
|
|
system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
|
|
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses
|
|
system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 53966.049383 # average ReadReq miss latency
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::total 53966.049383 # average ReadReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 55244.604317 # average WriteReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::total 55244.604317 # average WriteReq miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 54349.892009 # average overall miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::total 54349.892009 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 54349.892009 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::total 54349.892009 # average overall miss latency
|
|
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks
|
|
system.cpu2.dcache.writebacks::total 29 # number of writebacks
|
|
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 324 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 139 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::cpu2.data 463 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::cpu2.data 463 # number of overall MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 16837000 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 16837000 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 7401000 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 7401000 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 24238000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::total 24238000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 24238000 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::total 24238000 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002604 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002467 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 51966.049383 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 51966.049383 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53244.604317 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 53244.604317 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 52349.892009 # average overall mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 52349.892009 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 52349.892009 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 52349.892009 # average overall mshr miss latency
|
|
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu3.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu3.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu3.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu3.dtb.read_hits 124431 # DTB read hits
|
|
system.cpu3.dtb.read_misses 8 # DTB read misses
|
|
system.cpu3.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu3.dtb.read_accesses 124439 # DTB read accesses
|
|
system.cpu3.dtb.write_hits 56339 # DTB write hits
|
|
system.cpu3.dtb.write_misses 10 # DTB write misses
|
|
system.cpu3.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu3.dtb.write_accesses 56349 # DTB write accesses
|
|
system.cpu3.dtb.data_hits 180770 # DTB hits
|
|
system.cpu3.dtb.data_misses 18 # DTB misses
|
|
system.cpu3.dtb.data_acv 0 # DTB access violations
|
|
system.cpu3.dtb.data_accesses 180788 # DTB accesses
|
|
system.cpu3.itb.fetch_hits 499998 # ITB hits
|
|
system.cpu3.itb.fetch_misses 13 # ITB misses
|
|
system.cpu3.itb.fetch_acv 0 # ITB acv
|
|
system.cpu3.itb.fetch_accesses 500011 # ITB accesses
|
|
system.cpu3.itb.read_hits 0 # DTB read hits
|
|
system.cpu3.itb.read_misses 0 # DTB read misses
|
|
system.cpu3.itb.read_acv 0 # DTB read access violations
|
|
system.cpu3.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu3.itb.write_hits 0 # DTB write hits
|
|
system.cpu3.itb.write_misses 0 # DTB write misses
|
|
system.cpu3.itb.write_acv 0 # DTB write access violations
|
|
system.cpu3.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu3.itb.data_hits 0 # DTB hits
|
|
system.cpu3.itb.data_misses 0 # DTB misses
|
|
system.cpu3.itb.data_acv 0 # DTB access violations
|
|
system.cpu3.itb.data_accesses 0 # DTB accesses
|
|
system.cpu3.workload.num_syscalls 18 # Number of system calls
|
|
system.cpu3.numCycles 1458142 # number of cpu cycles simulated
|
|
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu3.committedInsts 499979 # Number of instructions committed
|
|
system.cpu3.committedOps 499979 # Number of ops (including micro ops) committed
|
|
system.cpu3.num_int_alu_accesses 474668 # Number of integer alu accesses
|
|
system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses
|
|
system.cpu3.num_func_calls 14357 # number of times a function call or return occured
|
|
system.cpu3.num_conditional_control_insts 38178 # number of instructions that are conditional controls
|
|
system.cpu3.num_int_insts 474668 # number of integer instructions
|
|
system.cpu3.num_fp_insts 32 # number of float instructions
|
|
system.cpu3.num_int_register_reads 654256 # number of times the integer registers were read
|
|
system.cpu3.num_int_register_writes 371524 # number of times the integer registers were written
|
|
system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read
|
|
system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written
|
|
system.cpu3.num_mem_refs 180788 # number of memory refs
|
|
system.cpu3.num_load_insts 124439 # Number of load instructions
|
|
system.cpu3.num_store_insts 56349 # Number of store instructions
|
|
system.cpu3.num_idle_cycles 0 # Number of idle cycles
|
|
system.cpu3.num_busy_cycles 1458142 # Number of busy cycles
|
|
system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
system.cpu3.idle_fraction 0 # Percentage of idle cycles
|
|
system.cpu3.icache.replacements 152 # number of replacements
|
|
system.cpu3.icache.tagsinuse 216.366465 # Cycle average of tags in use
|
|
system.cpu3.icache.total_refs 499535 # Total number of references to valid blocks.
|
|
system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu3.icache.avg_refs 1078.909287 # Average number of references to valid blocks.
|
|
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.icache.occ_blocks::cpu3.inst 216.366465 # Average occupied blocks per requestor
|
|
system.cpu3.icache.occ_percent::cpu3.inst 0.422591 # Average percentage of cache occupancy
|
|
system.cpu3.icache.occ_percent::total 0.422591 # Average percentage of cache occupancy
|
|
system.cpu3.icache.ReadReq_hits::cpu3.inst 499535 # number of ReadReq hits
|
|
system.cpu3.icache.ReadReq_hits::total 499535 # number of ReadReq hits
|
|
system.cpu3.icache.demand_hits::cpu3.inst 499535 # number of demand (read+write) hits
|
|
system.cpu3.icache.demand_hits::total 499535 # number of demand (read+write) hits
|
|
system.cpu3.icache.overall_hits::cpu3.inst 499535 # number of overall hits
|
|
system.cpu3.icache.overall_hits::total 499535 # number of overall hits
|
|
system.cpu3.icache.ReadReq_misses::cpu3.inst 463 # number of ReadReq misses
|
|
system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses
|
|
system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses
|
|
system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses
|
|
system.cpu3.icache.overall_misses::total 463 # number of overall misses
|
|
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 23153500 # number of ReadReq miss cycles
|
|
system.cpu3.icache.ReadReq_miss_latency::total 23153500 # number of ReadReq miss cycles
|
|
system.cpu3.icache.demand_miss_latency::cpu3.inst 23153500 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.demand_miss_latency::total 23153500 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.overall_miss_latency::cpu3.inst 23153500 # number of overall miss cycles
|
|
system.cpu3.icache.overall_miss_latency::total 23153500 # number of overall miss cycles
|
|
system.cpu3.icache.ReadReq_accesses::cpu3.inst 499998 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.ReadReq_accesses::total 499998 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.demand_accesses::cpu3.inst 499998 # number of demand (read+write) accesses
|
|
system.cpu3.icache.demand_accesses::total 499998 # number of demand (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::cpu3.inst 499998 # number of overall (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::total 499998 # number of overall (read+write) accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses
|
|
system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
|
|
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses
|
|
system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 50007.559395 # average ReadReq miss latency
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::total 50007.559395 # average ReadReq miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 50007.559395 # average overall miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::total 50007.559395 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 50007.559395 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::total 50007.559395 # average overall miss latency
|
|
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 463 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::cpu3.inst 463 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::cpu3.inst 463 # number of overall MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 22227500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::total 22227500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 22227500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::total 22227500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 22227500 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::total 22227500 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 48007.559395 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 48007.559395 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 48007.559395 # average overall mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::total 48007.559395 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 48007.559395 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::total 48007.559395 # average overall mshr miss latency
|
|
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.dcache.replacements 61 # number of replacements
|
|
system.cpu3.dcache.tagsinuse 273.485807 # Cycle average of tags in use
|
|
system.cpu3.dcache.total_refs 180307 # Total number of references to valid blocks.
|
|
system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
|
system.cpu3.dcache.avg_refs 389.431965 # Average number of references to valid blocks.
|
|
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.dcache.occ_blocks::cpu3.data 273.485807 # Average occupied blocks per requestor
|
|
system.cpu3.dcache.occ_percent::cpu3.data 0.534152 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.occ_percent::total 0.534152 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.ReadReq_hits::cpu3.data 124107 # number of ReadReq hits
|
|
system.cpu3.dcache.ReadReq_hits::total 124107 # number of ReadReq hits
|
|
system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits
|
|
system.cpu3.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
|
|
system.cpu3.dcache.demand_hits::cpu3.data 180307 # number of demand (read+write) hits
|
|
system.cpu3.dcache.demand_hits::total 180307 # number of demand (read+write) hits
|
|
system.cpu3.dcache.overall_hits::cpu3.data 180307 # number of overall hits
|
|
system.cpu3.dcache.overall_hits::total 180307 # number of overall hits
|
|
system.cpu3.dcache.ReadReq_misses::cpu3.data 324 # number of ReadReq misses
|
|
system.cpu3.dcache.ReadReq_misses::total 324 # number of ReadReq misses
|
|
system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses
|
|
system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses
|
|
system.cpu3.dcache.demand_misses::cpu3.data 463 # number of demand (read+write) misses
|
|
system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses
|
|
system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses
|
|
system.cpu3.dcache.overall_misses::total 463 # number of overall misses
|
|
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 17480000 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.ReadReq_miss_latency::total 17480000 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 7680500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::total 7680500 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::cpu3.data 25160500 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::total 25160500 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::cpu3.data 25160500 # number of overall miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::total 25160500 # number of overall miss cycles
|
|
system.cpu3.dcache.ReadReq_accesses::cpu3.data 124431 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.ReadReq_accesses::total 124431 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::cpu3.data 56339 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.demand_accesses::cpu3.data 180770 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.demand_accesses::total 180770 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::cpu3.data 180770 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::total 180770 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 # miss rate for demand accesses
|
|
system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
|
|
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses
|
|
system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 53950.617284 # average ReadReq miss latency
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::total 53950.617284 # average ReadReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 55255.395683 # average WriteReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::total 55255.395683 # average WriteReq miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 54342.332613 # average overall miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::total 54342.332613 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 54342.332613 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::total 54342.332613 # average overall miss latency
|
|
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks
|
|
system.cpu3.dcache.writebacks::total 29 # number of writebacks
|
|
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 324 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 139 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::cpu3.data 463 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::cpu3.data 463 # number of overall MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 16832000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::total 16832000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 7402500 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::total 7402500 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 24234500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::total 24234500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 24234500 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::total 24234500 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002604 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002467 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002561 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002561 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 51950.617284 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 51950.617284 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 53255.395683 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 53255.395683 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 52342.332613 # average overall mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 52342.332613 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52342.332613 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 52342.332613 # average overall mshr miss latency
|
|
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.replacements 0 # number of replacements
|
|
system.l2c.tagsinuse 1943.183618 # Cycle average of tags in use
|
|
system.l2c.total_refs 332 # Total number of references to valid blocks.
|
|
system.l2c.sampled_refs 2932 # Sample count of references to valid blocks.
|
|
system.l2c.avg_refs 0.113233 # Average number of references to valid blocks.
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.occ_blocks::writebacks 17.224365 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.inst 265.013770 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.data 216.489826 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu1.inst 265.008551 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu1.data 216.485888 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu2.inst 265.003220 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu2.data 216.481949 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu3.inst 264.998020 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu3.data 216.478029 # Average occupied blocks per requestor
|
|
system.l2c.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.data 0.003303 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.inst 0.004044 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.data 0.003303 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu2.inst 0.004044 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::total 0.029651 # Average percentage of cache occupancy
|
|
system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.inst 60 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu3.inst 60 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 116 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 116 # number of Writeback hits
|
|
system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 276 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 60 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 9 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 60 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 9 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 60 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 9 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.inst 60 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.data 9 # number of overall hits
|
|
system.l2c.overall_hits::total 276 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.inst 403 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 315 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 403 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 315 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.inst 403 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.data 315 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu3.inst 403 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu3.data 315 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 403 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 454 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 403 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 454 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 403 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 454 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.inst 403 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.data 454 # number of overall misses
|
|
system.l2c.overall_misses::total 3428 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 21102500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 16409500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 21114500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 16414000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.inst 21126000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.data 16417500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu3.inst 21137000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu3.data 16415000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 150136000 # number of ReadReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 7252500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 7253000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 7259500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu3.data 7259500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 29024500 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 21102500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 23662000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 21114500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 23667000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.inst 21126000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.data 23677000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.inst 21137000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.data 23674500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 179160500 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 21102500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 23662000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 21114500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 23667000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.inst 21126000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.data 23677000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.inst 21137000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.data 23674500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 179160500 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.inst 463 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 324 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 463 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 324 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.inst 463 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.data 324 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu3.inst 463 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu3.data 324 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 116 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.inst 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.data 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.inst 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.data 463 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.912325 # miss rate for ReadReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52363.523573 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52093.650794 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52393.300248 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52107.936508 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52421.836228 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.data 52119.047619 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu3.inst 52449.131514 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu3.data 52111.111111 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 52275.766017 # average ReadReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52176.258993 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52179.856115 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52226.618705 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52226.618705 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 52202.338129 # average ReadExReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 52363.523573 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 52118.942731 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 52393.300248 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 52129.955947 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.inst 52421.836228 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.data 52151.982379 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.inst 52449.131514 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.data 52146.475771 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 52263.856476 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 52363.523573 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 52118.942731 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 52393.300248 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 52129.955947 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.inst 52421.836228 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.data 52151.982379 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.inst 52449.131514 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.data 52146.475771 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 52263.856476 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.ReadReq_mshr_misses::cpu0.inst 403 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.data 315 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 403 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.data 315 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.inst 403 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.data 315 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu3.inst 403 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu3.data 315 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 2872 # number of ReadReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 139 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 139 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 139 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu3.data 139 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 556 # number of ReadExReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 403 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 454 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 403 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 454 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.inst 403 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.data 454 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.inst 403 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.data 454 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 3428 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 403 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 454 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 403 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 454 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.inst 403 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.data 454 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.inst 403 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.data 454 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 3428 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 16120000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 12600000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 16259000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12631500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 16249500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 12631500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 16282000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu3.data 12632000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 115405500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5560000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5580500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 5586500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 5587000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 22314000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 16120000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 18160000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 16259000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 18212000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.inst 16249500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.data 18218000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.inst 16282000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.data 18219000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 137719500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 16120000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 18160000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 16259000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 18212000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.inst 16249500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.data 18218000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.inst 16282000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.data 18219000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 137719500 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.972222 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.972222 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.972222 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.972222 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.912325 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.925486 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.925486 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40344.913151 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40100 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40321.339950 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40100 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40401.985112 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40101.587302 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 40182.973538 # average ReadReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40147.482014 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40190.647482 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40194.244604 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40133.093525 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40344.913151 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40114.537445 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40321.339950 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40127.753304 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40401.985112 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40129.955947 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 40174.883314 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40344.913151 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40114.537445 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40321.339950 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40127.753304 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40401.985112 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40129.955947 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 40174.883314 # average overall mshr miss latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|