7a2ecf9e26
util/m5/Makefile.alpha: Clean up to make it a bit easier to muck with util/m5/Makefile.alpha: Make the makefile more reasonable util/m5/Makefile.alpha: Remove authors from copyright. util/m5/Makefile.alpha: Updated Authors from bk prs info util/m5/Makefile.alpha: bk cp Makefile Makefile.alpha src/arch/sparc/tlb.cc: Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate src/arch/alpha/isa/decoder.isa: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: Rename AlphaPseudo -> PseudoInst since it's all generic src/arch/sparc/isa/bitfields.isa: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/includes.isa: src/arch/sparc/isa/operands.isa: Add support for pseudo instructions in sparc util/m5/Makefile.alpha: util/m5/Makefile.sparc: split off alpha make file and sparc make file for m5 app util/m5/m5.c: ivle and ivlb aren't used anymore util/m5/m5op.h: stdint seems like a more generic better fit here util/m5/m5op_alpha.S: move the op ids into their own header file since we can share them between sparc and alpha --HG-- rename : util/m5/Makefile => util/m5/Makefile.sparc rename : util/m5/m5op.S => util/m5/m5op_alpha.S extra : convert_revision : 490ba2e8b8bc6e28bfc009cedec6b686b28e7834
315 lines
8.4 KiB
C++
315 lines
8.4 KiB
C++
/*
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* Copyright (c) 2003-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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*/
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#include <errno.h>
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#include <fcntl.h>
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#include <unistd.h>
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#include <fstream>
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#include <string>
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#include "arch/vtophys.hh"
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#include "base/annotate.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/quiesce_event.hh"
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#include "arch/kernel_stats.hh"
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#include "sim/pseudo_inst.hh"
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#include "sim/serialize.hh"
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#include "sim/sim_exit.hh"
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#include "sim/stat_control.hh"
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#include "sim/stats.hh"
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#include "sim/system.hh"
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#include "sim/debug.hh"
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#include "sim/vptr.hh"
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using namespace std;
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using namespace Stats;
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using namespace TheISA;
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namespace PseudoInst
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{
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void
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arm(ThreadContext *tc)
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{
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if (tc->getKernelStats())
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tc->getKernelStats()->arm();
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}
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void
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quiesce(ThreadContext *tc)
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{
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if (!tc->getCpuPtr()->params->do_quiesce)
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return;
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DPRINTF(Quiesce, "%s: quiesce()\n", tc->getCpuPtr()->name());
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tc->suspend();
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if (tc->getKernelStats())
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tc->getKernelStats()->quiesce();
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}
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void
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quiesceNs(ThreadContext *tc, uint64_t ns)
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{
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if (!tc->getCpuPtr()->params->do_quiesce || ns == 0)
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return;
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EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
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Tick resume = curTick + Clock::Int::ns * ns;
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if (quiesceEvent->scheduled())
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quiesceEvent->reschedule(resume);
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else
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quiesceEvent->schedule(resume);
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DPRINTF(Quiesce, "%s: quiesceNs(%d) until %d\n",
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tc->getCpuPtr()->name(), ns, resume);
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tc->suspend();
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if (tc->getKernelStats())
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tc->getKernelStats()->quiesce();
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}
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void
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quiesceCycles(ThreadContext *tc, uint64_t cycles)
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{
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if (!tc->getCpuPtr()->params->do_quiesce || cycles == 0)
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return;
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EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
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Tick resume = curTick + tc->getCpuPtr()->cycles(cycles);
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if (quiesceEvent->scheduled())
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quiesceEvent->reschedule(resume);
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else
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quiesceEvent->schedule(resume);
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DPRINTF(Quiesce, "%s: quiesceCycles(%d) until %d\n",
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tc->getCpuPtr()->name(), cycles, resume);
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tc->suspend();
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if (tc->getKernelStats())
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tc->getKernelStats()->quiesce();
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}
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uint64_t
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quiesceTime(ThreadContext *tc)
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{
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return (tc->readLastActivate() - tc->readLastSuspend()) / Clock::Int::ns;
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}
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void
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m5exit_old(ThreadContext *tc)
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{
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exitSimLoop("m5_exit_old instruction encountered");
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}
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void
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m5exit(ThreadContext *tc, Tick delay)
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{
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Tick when = curTick + delay * Clock::Int::ns;
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schedExitSimLoop("m5_exit instruction encountered", when);
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}
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void
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loadsymbol(ThreadContext *tc)
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{
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const string &filename = tc->getCpuPtr()->system->params()->symbolfile;
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if (filename.empty()) {
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return;
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}
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std::string buffer;
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ifstream file(filename.c_str());
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if (!file)
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fatal("file error: Can't open symbol table file %s\n", filename);
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while (!file.eof()) {
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getline(file, buffer);
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if (buffer.empty())
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continue;
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int idx = buffer.find(' ');
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if (idx == string::npos)
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continue;
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string address = "0x" + buffer.substr(0, idx);
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eat_white(address);
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if (address.empty())
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continue;
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// Skip over letter and space
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string symbol = buffer.substr(idx + 3);
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eat_white(symbol);
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if (symbol.empty())
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continue;
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Addr addr;
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if (!to_number(address, addr))
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continue;
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if (!tc->getSystemPtr()->kernelSymtab->insert(addr, symbol))
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continue;
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DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
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}
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file.close();
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}
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void
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resetstats(ThreadContext *tc, Tick delay, Tick period)
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{
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if (!tc->getCpuPtr()->params->do_statistics_insts)
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return;
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Tick when = curTick + delay * Clock::Int::ns;
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Tick repeat = period * Clock::Int::ns;
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Stats::StatEvent(false, true, when, repeat);
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}
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void
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dumpstats(ThreadContext *tc, Tick delay, Tick period)
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{
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if (!tc->getCpuPtr()->params->do_statistics_insts)
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return;
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Tick when = curTick + delay * Clock::Int::ns;
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Tick repeat = period * Clock::Int::ns;
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Stats::StatEvent(true, false, when, repeat);
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}
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void
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addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr)
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{
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char symb[100];
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CopyStringOut(tc, symb, symbolAddr, 100);
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std::string symbol(symb);
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DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
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tc->getSystemPtr()->kernelSymtab->insert(addr,symbol);
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}
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void
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anBegin(ThreadContext *tc, uint64_t cur)
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{
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Annotate::annotations.add(tc->getSystemPtr(), 0, cur >> 32, cur &
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0xFFFFFFFF, 0,0);
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}
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void
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anWait(ThreadContext *tc, uint64_t cur, uint64_t wait)
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{
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Annotate::annotations.add(tc->getSystemPtr(), 0, cur >> 32, cur &
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0xFFFFFFFF, wait >> 32, wait & 0xFFFFFFFF);
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}
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void
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dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
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{
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if (!tc->getCpuPtr()->params->do_statistics_insts)
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return;
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Tick when = curTick + delay * Clock::Int::ns;
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Tick repeat = period * Clock::Int::ns;
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Stats::StatEvent(true, true, when, repeat);
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}
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void
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m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
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{
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if (!tc->getCpuPtr()->params->do_checkpoint_insts)
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return;
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Tick when = curTick + delay * Clock::Int::ns;
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Tick repeat = period * Clock::Int::ns;
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schedExitSimLoop("checkpoint", when, repeat);
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}
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uint64_t
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readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
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{
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const string &file = tc->getSystemPtr()->params()->readfile;
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if (file.empty()) {
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return ULL(0);
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}
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uint64_t result = 0;
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int fd = ::open(file.c_str(), O_RDONLY, 0);
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if (fd < 0)
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panic("could not open file %s\n", file);
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if (::lseek(fd, offset, SEEK_SET) < 0)
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panic("could not seek: %s", strerror(errno));
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char *buf = new char[len];
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char *p = buf;
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while (len > 0) {
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int bytes = ::read(fd, p, len);
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if (bytes <= 0)
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break;
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p += bytes;
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result += bytes;
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len -= bytes;
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}
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close(fd);
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CopyIn(tc, vaddr, buf, result);
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delete [] buf;
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return result;
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}
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void debugbreak(ThreadContext *tc)
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{
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debug_break();
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}
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void switchcpu(ThreadContext *tc)
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{
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exitSimLoop("switchcpu");
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}
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}
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