589 lines
16 KiB
C++
589 lines
16 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Nathan Binkert
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*/
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#include "arch/alpha/faults.hh"
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#include "arch/alpha/isa_traits.hh"
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#include "arch/alpha/kernel_stats.hh"
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#include "arch/alpha/osfpal.hh"
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#include "arch/alpha/tlb.hh"
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#include "arch/alpha/kgdb.h"
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#include "base/remote_gdb.hh"
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#include "base/stats/events.hh"
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#include "config/full_system.hh"
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#include "cpu/base.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/thread_context.hh"
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#include "sim/debug.hh"
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#include "sim/sim_exit.hh"
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#if FULL_SYSTEM
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using namespace EV5;
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////////////////////////////////////////////////////////////////////////
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//
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// Machine dependent functions
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//
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void
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AlphaISA::initCPU(ThreadContext *tc, int cpuId)
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{
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initIPRs(tc, cpuId);
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tc->setIntReg(16, cpuId);
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tc->setIntReg(0, cpuId);
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AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault;
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tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect());
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tc->setNextPC(tc->readPC() + sizeof(MachInst));
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delete reset;
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}
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////////////////////////////////////////////////////////////////////////
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//
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//
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//
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void
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AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
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{
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for (int i = 0; i < NumInternalProcRegs; ++i) {
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tc->setMiscRegNoEffect(i, 0);
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}
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tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
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tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
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tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
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}
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template <class CPU>
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void
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AlphaISA::processInterrupts(CPU *cpu)
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{
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//Check if there are any outstanding interrupts
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//Handle the interrupts
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int ipl = 0;
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int summary = 0;
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if (cpu->readMiscRegNoEffect(IPR_ASTRR))
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panic("asynchronous traps not implemented\n");
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if (cpu->readMiscRegNoEffect(IPR_SIRR)) {
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for (int i = INTLEVEL_SOFTWARE_MIN;
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i < INTLEVEL_SOFTWARE_MAX; i++) {
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if (cpu->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
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// See table 4-19 of the 21164 hardware reference
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ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
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summary |= (ULL(1) << i);
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}
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}
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}
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uint64_t interrupts = cpu->intr_status();
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if (interrupts) {
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for (int i = INTLEVEL_EXTERNAL_MIN;
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i < INTLEVEL_EXTERNAL_MAX; i++) {
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if (interrupts & (ULL(1) << i)) {
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// See table 4-19 of the 21164 hardware reference
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ipl = i;
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summary |= (ULL(1) << i);
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}
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}
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}
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if (ipl && ipl > cpu->readMiscRegNoEffect(IPR_IPLR)) {
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cpu->setMiscRegNoEffect(IPR_ISR, summary);
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cpu->setMiscRegNoEffect(IPR_INTID, ipl);
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cpu->trap(new InterruptFault);
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DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
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cpu->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
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}
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}
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template <class CPU>
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void
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AlphaISA::zeroRegisters(CPU *cpu)
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{
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// Insure ISA semantics
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// (no longer very clean due to the change in setIntReg() in the
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// cpu model. Consider changing later.)
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cpu->thread->setIntReg(ZeroReg, 0);
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cpu->thread->setFloatReg(ZeroReg, 0.0);
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}
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Fault
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SimpleThread::hwrei()
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{
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if (!(readPC() & 0x3))
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return new UnimplementedOpcodeFault;
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setNextPC(readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
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if (!misspeculating()) {
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if (kernelStats)
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kernelStats->hwrei();
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}
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// FIXME: XXX check for interrupts? XXX
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return NoFault;
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}
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int
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AlphaISA::MiscRegFile::getInstAsid()
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{
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return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
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}
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int
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AlphaISA::MiscRegFile::getDataAsid()
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{
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return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
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}
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AlphaISA::MiscReg
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AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
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{
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uint64_t retval = 0; // return value, default 0
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switch (idx) {
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case AlphaISA::IPR_PALtemp0:
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case AlphaISA::IPR_PALtemp1:
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case AlphaISA::IPR_PALtemp2:
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case AlphaISA::IPR_PALtemp3:
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case AlphaISA::IPR_PALtemp4:
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case AlphaISA::IPR_PALtemp5:
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case AlphaISA::IPR_PALtemp6:
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case AlphaISA::IPR_PALtemp7:
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case AlphaISA::IPR_PALtemp8:
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case AlphaISA::IPR_PALtemp9:
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case AlphaISA::IPR_PALtemp10:
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case AlphaISA::IPR_PALtemp11:
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case AlphaISA::IPR_PALtemp12:
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case AlphaISA::IPR_PALtemp13:
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case AlphaISA::IPR_PALtemp14:
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case AlphaISA::IPR_PALtemp15:
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case AlphaISA::IPR_PALtemp16:
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case AlphaISA::IPR_PALtemp17:
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case AlphaISA::IPR_PALtemp18:
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case AlphaISA::IPR_PALtemp19:
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case AlphaISA::IPR_PALtemp20:
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case AlphaISA::IPR_PALtemp21:
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case AlphaISA::IPR_PALtemp22:
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case AlphaISA::IPR_PALtemp23:
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case AlphaISA::IPR_PAL_BASE:
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case AlphaISA::IPR_IVPTBR:
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case AlphaISA::IPR_DC_MODE:
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case AlphaISA::IPR_MAF_MODE:
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case AlphaISA::IPR_ISR:
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case AlphaISA::IPR_EXC_ADDR:
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case AlphaISA::IPR_IC_PERR_STAT:
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case AlphaISA::IPR_DC_PERR_STAT:
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case AlphaISA::IPR_MCSR:
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case AlphaISA::IPR_ASTRR:
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case AlphaISA::IPR_ASTER:
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case AlphaISA::IPR_SIRR:
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case AlphaISA::IPR_ICSR:
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case AlphaISA::IPR_ICM:
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case AlphaISA::IPR_DTB_CM:
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case AlphaISA::IPR_IPLR:
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case AlphaISA::IPR_INTID:
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case AlphaISA::IPR_PMCTR:
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// no side-effect
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retval = ipr[idx];
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break;
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case AlphaISA::IPR_CC:
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retval |= ipr[idx] & ULL(0xffffffff00000000);
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retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
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break;
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case AlphaISA::IPR_VA:
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retval = ipr[idx];
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break;
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case AlphaISA::IPR_VA_FORM:
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case AlphaISA::IPR_MM_STAT:
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case AlphaISA::IPR_IFAULT_VA_FORM:
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case AlphaISA::IPR_EXC_MASK:
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case AlphaISA::IPR_EXC_SUM:
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retval = ipr[idx];
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break;
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case AlphaISA::IPR_DTB_PTE:
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{
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AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating());
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retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
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retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
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retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
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retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
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retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
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retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
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retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
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}
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break;
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// write only registers
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case AlphaISA::IPR_HWINT_CLR:
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case AlphaISA::IPR_SL_XMIT:
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case AlphaISA::IPR_DC_FLUSH:
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case AlphaISA::IPR_IC_FLUSH:
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case AlphaISA::IPR_ALT_MODE:
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case AlphaISA::IPR_DTB_IA:
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case AlphaISA::IPR_DTB_IAP:
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case AlphaISA::IPR_ITB_IA:
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case AlphaISA::IPR_ITB_IAP:
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panic("Tried to read write only register %d\n", idx);
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break;
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default:
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// invalid IPR
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panic("Tried to read from invalid ipr %d\n", idx);
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break;
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}
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return retval;
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}
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#ifdef DEBUG
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// Cause the simulator to break when changing to the following IPL
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int break_ipl = -1;
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#endif
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void
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AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
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{
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uint64_t old;
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if (tc->misspeculating())
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return;
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switch (idx) {
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case AlphaISA::IPR_PALtemp0:
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case AlphaISA::IPR_PALtemp1:
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case AlphaISA::IPR_PALtemp2:
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case AlphaISA::IPR_PALtemp3:
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case AlphaISA::IPR_PALtemp4:
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case AlphaISA::IPR_PALtemp5:
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case AlphaISA::IPR_PALtemp6:
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case AlphaISA::IPR_PALtemp7:
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case AlphaISA::IPR_PALtemp8:
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case AlphaISA::IPR_PALtemp9:
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case AlphaISA::IPR_PALtemp10:
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case AlphaISA::IPR_PALtemp11:
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case AlphaISA::IPR_PALtemp12:
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case AlphaISA::IPR_PALtemp13:
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case AlphaISA::IPR_PALtemp14:
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case AlphaISA::IPR_PALtemp15:
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case AlphaISA::IPR_PALtemp16:
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case AlphaISA::IPR_PALtemp17:
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case AlphaISA::IPR_PALtemp18:
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case AlphaISA::IPR_PALtemp19:
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case AlphaISA::IPR_PALtemp20:
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case AlphaISA::IPR_PALtemp21:
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case AlphaISA::IPR_PALtemp22:
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case AlphaISA::IPR_PAL_BASE:
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case AlphaISA::IPR_IC_PERR_STAT:
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case AlphaISA::IPR_DC_PERR_STAT:
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case AlphaISA::IPR_PMCTR:
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// write entire quad w/ no side-effect
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_CC_CTL:
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// This IPR resets the cycle counter. We assume this only
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// happens once... let's verify that.
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assert(ipr[idx] == 0);
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ipr[idx] = 1;
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break;
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case AlphaISA::IPR_CC:
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// This IPR only writes the upper 64 bits. It's ok to write
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// all 64 here since we mask out the lower 32 in rpcc (see
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// isa_desc).
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_PALtemp23:
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// write entire quad w/ no side-effect
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old = ipr[idx];
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ipr[idx] = val;
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if (tc->getKernelStats())
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tc->getKernelStats()->context(old, val, tc);
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break;
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case AlphaISA::IPR_DTB_PTE:
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// write entire quad w/ no side-effect, tag is forthcoming
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_EXC_ADDR:
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// second least significant bit in PC is always zero
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ipr[idx] = val & ~2;
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break;
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case AlphaISA::IPR_ASTRR:
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case AlphaISA::IPR_ASTER:
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// only write least significant four bits - privilege mask
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ipr[idx] = val & 0xf;
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break;
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case AlphaISA::IPR_IPLR:
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#ifdef DEBUG
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if (break_ipl != -1 && break_ipl == (val & 0x1f))
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debug_break();
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#endif
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// only write least significant five bits - interrupt level
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ipr[idx] = val & 0x1f;
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if (tc->getKernelStats())
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tc->getKernelStats()->swpipl(ipr[idx]);
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break;
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case AlphaISA::IPR_DTB_CM:
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if (val & 0x18) {
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if (tc->getKernelStats())
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tc->getKernelStats()->mode(TheISA::Kernel::user, tc);
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} else {
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if (tc->getKernelStats())
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tc->getKernelStats()->mode(TheISA::Kernel::kernel, tc);
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}
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case AlphaISA::IPR_ICM:
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// only write two mode bits - processor mode
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ipr[idx] = val & 0x18;
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break;
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case AlphaISA::IPR_ALT_MODE:
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// only write two mode bits - processor mode
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ipr[idx] = val & 0x18;
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break;
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case AlphaISA::IPR_MCSR:
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// more here after optimization...
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_SIRR:
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// only write software interrupt mask
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ipr[idx] = val & 0x7fff0;
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break;
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case AlphaISA::IPR_ICSR:
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ipr[idx] = val & ULL(0xffffff0300);
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break;
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case AlphaISA::IPR_IVPTBR:
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case AlphaISA::IPR_MVPTBR:
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ipr[idx] = val & ULL(0xffffffffc0000000);
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break;
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case AlphaISA::IPR_DC_TEST_CTL:
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ipr[idx] = val & 0x1ffb;
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break;
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case AlphaISA::IPR_DC_MODE:
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case AlphaISA::IPR_MAF_MODE:
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ipr[idx] = val & 0x3f;
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break;
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case AlphaISA::IPR_ITB_ASN:
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ipr[idx] = val & 0x7f0;
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break;
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case AlphaISA::IPR_DTB_ASN:
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ipr[idx] = val & ULL(0xfe00000000000000);
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break;
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case AlphaISA::IPR_EXC_SUM:
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case AlphaISA::IPR_EXC_MASK:
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// any write to this register clears it
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ipr[idx] = 0;
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break;
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case AlphaISA::IPR_INTID:
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case AlphaISA::IPR_SL_RCV:
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case AlphaISA::IPR_MM_STAT:
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case AlphaISA::IPR_ITB_PTE_TEMP:
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case AlphaISA::IPR_DTB_PTE_TEMP:
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// read-only registers
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panic("Tried to write read only ipr %d\n", idx);
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case AlphaISA::IPR_HWINT_CLR:
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case AlphaISA::IPR_SL_XMIT:
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case AlphaISA::IPR_DC_FLUSH:
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case AlphaISA::IPR_IC_FLUSH:
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// the following are write only
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_DTB_IA:
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// really a control write
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ipr[idx] = 0;
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tc->getDTBPtr()->flushAll();
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break;
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case AlphaISA::IPR_DTB_IAP:
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// really a control write
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ipr[idx] = 0;
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tc->getDTBPtr()->flushProcesses();
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break;
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case AlphaISA::IPR_DTB_IS:
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// really a control write
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ipr[idx] = val;
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tc->getDTBPtr()->flushAddr(val,
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DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
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break;
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case AlphaISA::IPR_DTB_TAG: {
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struct AlphaISA::PTE pte;
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// FIXME: granularity hints NYI...
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if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
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panic("PTE GH field != 0");
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// write entire quad
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ipr[idx] = val;
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// construct PTE for new entry
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pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
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pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
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pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
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pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
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pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
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pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
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pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
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// insert new TAG/PTE value into data TLB
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tc->getDTBPtr()->insert(val, pte);
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}
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break;
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case AlphaISA::IPR_ITB_PTE: {
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struct AlphaISA::PTE pte;
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|
|
// FIXME: granularity hints NYI...
|
|
if (ITB_PTE_GH(val) != 0)
|
|
panic("PTE GH field != 0");
|
|
|
|
// write entire quad
|
|
ipr[idx] = val;
|
|
|
|
// construct PTE for new entry
|
|
pte.ppn = ITB_PTE_PPN(val);
|
|
pte.xre = ITB_PTE_XRE(val);
|
|
pte.xwe = 0;
|
|
pte.fonr = ITB_PTE_FONR(val);
|
|
pte.fonw = ITB_PTE_FONW(val);
|
|
pte.asma = ITB_PTE_ASMA(val);
|
|
pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
|
|
|
|
// insert new TAG/PTE value into data TLB
|
|
tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
|
|
}
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_IA:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
tc->getITBPtr()->flushAll();
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_IAP:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
tc->getITBPtr()->flushProcesses();
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_IS:
|
|
// really a control write
|
|
ipr[idx] = val;
|
|
|
|
tc->getITBPtr()->flushAddr(val,
|
|
ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
|
|
break;
|
|
|
|
default:
|
|
// invalid IPR
|
|
panic("Tried to write to invalid ipr %d\n", idx);
|
|
}
|
|
|
|
// no error...
|
|
}
|
|
|
|
|
|
void
|
|
AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
|
|
{
|
|
for (int i = 0; i < NumInternalProcRegs; ++i) {
|
|
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
|
|
}
|
|
}
|
|
|
|
|
|
/**
|
|
* Check for special simulator handling of specific PAL calls.
|
|
* If return value is false, actual PAL call will be suppressed.
|
|
*/
|
|
bool
|
|
SimpleThread::simPalCheck(int palFunc)
|
|
{
|
|
if (kernelStats)
|
|
kernelStats->callpal(palFunc, tc);
|
|
|
|
switch (palFunc) {
|
|
case PAL::halt:
|
|
halt();
|
|
if (--System::numSystemsRunning == 0)
|
|
exitSimLoop("all cpus halted");
|
|
break;
|
|
|
|
case PAL::bpt:
|
|
case PAL::bugchk:
|
|
if (system->breakpoint())
|
|
return false;
|
|
break;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
#endif // FULL_SYSTEM
|