201 lines
7.9 KiB
C++
201 lines
7.9 KiB
C++
/*
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* Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Sooraj Puthoor
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*/
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#include "gpu-compute/local_memory_pipeline.hh"
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#include "debug/GPUPort.hh"
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#include "gpu-compute/compute_unit.hh"
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#include "gpu-compute/gpu_dyn_inst.hh"
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#include "gpu-compute/shader.hh"
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#include "gpu-compute/vector_register_file.hh"
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#include "gpu-compute/wavefront.hh"
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LocalMemPipeline::LocalMemPipeline(const ComputeUnitParams* p) :
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computeUnit(nullptr), lmQueueSize(p->local_mem_queue_size)
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{
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}
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void
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LocalMemPipeline::init(ComputeUnit *cu)
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{
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computeUnit = cu;
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_name = computeUnit->name() + ".LocalMemPipeline";
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}
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void
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LocalMemPipeline::exec()
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{
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// apply any returned shared (LDS) memory operations
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GPUDynInstPtr m = !lmReturnedRequests.empty() ?
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lmReturnedRequests.front() : nullptr;
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bool accessVrf = true;
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if ((m) && (m->m_op==Enums::MO_LD || MO_A(m->m_op))) {
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Wavefront *w = computeUnit->wfList[m->simdId][m->wfSlotId];
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accessVrf =
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w->computeUnit->vrf[m->simdId]->
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vrfOperandAccessReady(m->seqNum(), w, m,
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VrfAccessType::WRITE);
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}
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if (!lmReturnedRequests.empty() && m->latency.rdy() && accessVrf &&
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computeUnit->locMemToVrfBus.rdy() && (computeUnit->shader->coissue_return
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|| computeUnit->wfWait.at(m->pipeId).rdy())) {
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if (m->v_type == VT_32 && m->m_type == Enums::M_U8)
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doSmReturn<uint32_t, uint8_t>(m);
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else if (m->v_type == VT_32 && m->m_type == Enums::M_U16)
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doSmReturn<uint32_t, uint16_t>(m);
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else if (m->v_type == VT_32 && m->m_type == Enums::M_U32)
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doSmReturn<uint32_t, uint32_t>(m);
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else if (m->v_type == VT_32 && m->m_type == Enums::M_S8)
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doSmReturn<int32_t, int8_t>(m);
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else if (m->v_type == VT_32 && m->m_type == Enums::M_S16)
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doSmReturn<int32_t, int16_t>(m);
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else if (m->v_type == VT_32 && m->m_type == Enums::M_S32)
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doSmReturn<int32_t, int32_t>(m);
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else if (m->v_type == VT_32 && m->m_type == Enums::M_F16)
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doSmReturn<float, Float16>(m);
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else if (m->v_type == VT_32 && m->m_type == Enums::M_F32)
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doSmReturn<float, float>(m);
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else if (m->v_type == VT_64 && m->m_type == Enums::M_U8)
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doSmReturn<uint64_t, uint8_t>(m);
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else if (m->v_type == VT_64 && m->m_type == Enums::M_U16)
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doSmReturn<uint64_t, uint16_t>(m);
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else if (m->v_type == VT_64 && m->m_type == Enums::M_U32)
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doSmReturn<uint64_t, uint32_t>(m);
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else if (m->v_type == VT_64 && m->m_type == Enums::M_U64)
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doSmReturn<uint64_t, uint64_t>(m);
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else if (m->v_type == VT_64 && m->m_type == Enums::M_S8)
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doSmReturn<int64_t, int8_t>(m);
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else if (m->v_type == VT_64 && m->m_type == Enums::M_S16)
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doSmReturn<int64_t, int16_t>(m);
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else if (m->v_type == VT_64 && m->m_type == Enums::M_S32)
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doSmReturn<int64_t, int32_t>(m);
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else if (m->v_type == VT_64 && m->m_type == Enums::M_S64)
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doSmReturn<int64_t, int64_t>(m);
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else if (m->v_type == VT_64 && m->m_type == Enums::M_F16)
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doSmReturn<double, Float16>(m);
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else if (m->v_type == VT_64 && m->m_type == Enums::M_F32)
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doSmReturn<double, float>(m);
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else if (m->v_type == VT_64 && m->m_type == Enums::M_F64)
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doSmReturn<double, double>(m);
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}
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// If pipeline has executed a local memory instruction
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// execute local memory packet and issue the packets
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// to LDS
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if (!lmIssuedRequests.empty() && lmReturnedRequests.size() < lmQueueSize) {
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GPUDynInstPtr m = lmIssuedRequests.front();
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bool returnVal = computeUnit->sendToLds(m);
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if (!returnVal) {
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DPRINTF(GPUPort, "packet was nack'd and put in retry queue");
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}
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lmIssuedRequests.pop();
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}
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}
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template<typename c0, typename c1>
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void
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LocalMemPipeline::doSmReturn(GPUDynInstPtr m)
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{
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lmReturnedRequests.pop();
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Wavefront *w = computeUnit->wfList[m->simdId][m->wfSlotId];
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// Return data to registers
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if (m->m_op == Enums::MO_LD || MO_A(m->m_op)) {
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std::vector<uint32_t> regVec;
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for (int k = 0; k < m->n_reg; ++k) {
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int dst = m->dst_reg+k;
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if (m->n_reg > MAX_REGS_FOR_NON_VEC_MEM_INST)
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dst = m->dst_reg_vec[k];
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// virtual->physical VGPR mapping
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int physVgpr = w->remap(dst,sizeof(c0),1);
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// save the physical VGPR index
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regVec.push_back(physVgpr);
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c1 *p1 = &((c1*)m->d_data)[k * VSZ];
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for (int i = 0; i < VSZ; ++i) {
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if (m->exec_mask[i]) {
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// write the value into the physical VGPR. This is a purely
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// functional operation. No timing is modeled.
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w->computeUnit->vrf[w->simdId]->write<c0>(physVgpr,
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*p1, i);
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}
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++p1;
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}
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}
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// Schedule the write operation of the load data on the VRF. This simply
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// models the timing aspect of the VRF write operation. It does not
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// modify the physical VGPR.
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loadVrfBankConflictCycles +=
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w->computeUnit->vrf[w->simdId]->exec(m->seqNum(), w,
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regVec, sizeof(c0), m->time);
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}
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// Decrement outstanding request count
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computeUnit->shader->ScheduleAdd(&w->outstanding_reqs, m->time, -1);
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if (m->m_op == Enums::MO_ST || MO_A(m->m_op) || MO_ANR(m->m_op)
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|| MO_H(m->m_op)) {
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computeUnit->shader->ScheduleAdd(&w->outstanding_reqs_wr_lm,
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m->time, -1);
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}
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if (m->m_op == Enums::MO_LD || MO_A(m->m_op) || MO_ANR(m->m_op)) {
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computeUnit->shader->ScheduleAdd(&w->outstanding_reqs_rd_lm,
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m->time, -1);
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}
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// Mark write bus busy for appropriate amount of time
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computeUnit->locMemToVrfBus.set(m->time);
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if (computeUnit->shader->coissue_return == 0)
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w->computeUnit->wfWait.at(m->pipeId).set(m->time);
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}
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void
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LocalMemPipeline::regStats()
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{
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loadVrfBankConflictCycles
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.name(name() + ".load_vrf_bank_conflict_cycles")
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.desc("total number of cycles LDS data are delayed before updating "
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"the VRF")
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;
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}
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