59 lines
2.9 KiB
Python
59 lines
2.9 KiB
Python
# Copyright (c) 2005-2008 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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from m5.params import *
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from m5.proxy import *
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from MemObject import *
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class PhysicalMemory(MemObject):
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type = 'PhysicalMemory'
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port = VectorPort("the access port")
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range = Param.AddrRange(AddrRange('128MB'), "Device Address")
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file = Param.String('', "memory mapped file")
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latency = Param.Latency('30ns', "latency of an access")
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latency_var = Param.Latency('0ns', "access variablity")
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zero = Param.Bool(False, "zero initialize memory")
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null = Param.Bool(False, "do not store data, always return zero")
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class DRAMMemory(PhysicalMemory):
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type = 'DRAMMemory'
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# Many of these should be observed from the configuration
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cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed")
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mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)")
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mem_actpolicy = Param.String("open", "Open/Close policy")
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memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct")
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bus_width = Param.Int(16, "")
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act_lat = Param.Latency("2ns", "RAS to CAS delay")
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cas_lat = Param.Latency("1ns", "CAS delay")
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war_lat = Param.Latency("2ns", "write after read delay")
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pre_lat = Param.Latency("2ns", "precharge delay")
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dpl_lat = Param.Latency("2ns", "data in to precharge delay")
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trc_lat = Param.Latency("6ns", "row cycle delay")
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num_banks = Param.Int(4, "Number of Banks")
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num_cpus = Param.Int(4, "Number of CPUs connected to DRAM")
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