gem5/util/cpt_upgraders/arm-gem5-gic-ext.py
Karthik Sangaiah 6fa936b021 dev, arm: Add gem5 extensions to support more than 8 cores
Previous ARM-based simulations were limited to 8 cores due to
limitations in GICv2 and earlier. This changeset adds a set of
gem5-specific extensions that enable support for up to 256 cores.

When the gem5 extensions are enabled, the GIC uses CPU IDs instead of
a CPU bitmask in the GIC's register interface. To OS can enable the
extensions by setting bit 0x200 in ICDICTR.

This changeset is based on previous work by Matt Evans.
2015-09-18 16:49:28 +01:00

77 lines
3.3 KiB
Python

# Copyright (c) 2015 ARM Limited
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# Authors: Andreas Sandberg
#
def upgrader(cpt):
"""The gem5 GIC extensions change the size of many GIC data
structures. Resize them to match the new GIC."""
import re
if cpt.get('root','isa') != 'arm':
return
old_cpu_max = 8
new_cpu_max = 256
sgi_max = 16
ppi_max = 16
per_cpu_regs = (
("iccrpr", [ "0xff", ]),
("cpuEnabled", [ "false", ]),
("cpuPriority", [ "0xff", ]),
("cpuBpr", [ "0", ]),
("cpuHighestInt", [ "1023", ]),
("cpuPpiPending", [ "0", ]),
("cpuPpiActive", [ "0", ] ),
("interrupt_time", [ "0", ]),
("*bankedIntPriority", ["0", ] * (sgi_max + ppi_max)),
)
new_per_cpu_regs = (
("cpuSgiPendingExt", "0"),
("cpuSgiActiveExt", "0"),
)
for sec in cpt.sections():
if re.search('.*\.gic$', sec):
for reg, default in per_cpu_regs:
value = cpt.get(sec, reg).split(" ")
assert len(value) / len(default) == old_cpu_max, \
"GIC register size mismatch"
value += [ " ".join(default), ] * (new_cpu_max - old_cpu_max)
cpt.set(sec, reg, " ".join(value))
for reg, default in new_per_cpu_regs:
cpt.set(sec, reg, " ".join([ default, ] * new_cpu_max))