19ca97af79
succesfully but there are some minor quirks to iron out. Who would've known a DELAY SLOT introduces that much complexity?! arrgh! Anyways, a lot of this stuff had to do with my project at MIPS and me needing to know how I was going to get this working for the MIPS ISA. So I figured I would try to touch it up and throw it in here (I hate to introduce non-completely working components... ) src/arch/alpha/isa/mem.isa: spacing src/arch/mips/faults.cc: src/arch/mips/faults.hh: Gabe really authored this src/arch/mips/isa/decoder.isa: add StoreConditional Flag to instruction src/arch/mips/isa/formats/basic.isa: Steven really did this file src/arch/mips/isa/formats/branch.isa: fix bug for uncond/cond control src/arch/mips/isa/formats/mem.isa: Adjust O3CPU memory access to use new memory model interface. src/arch/mips/isa/formats/util.isa: update LoadStoreBase template src/arch/mips/isa_traits.cc: update SERIALIZE partially src/arch/mips/process.cc: src/arch/mips/process.hh: no need for this for NOW. ASID/Virtual addressing handles it src/arch/mips/regfile/misc_regfile.hh: add in clear() function and comments for future usage of special misc. regs src/cpu/base_dyn_inst.hh: add in nextNPC variable and supporting functions. add isCondDelaySlot function Update predTaken and mispredicted functions src/cpu/base_dyn_inst_impl.hh: init nextNPC src/cpu/o3/SConscript: add MIPS files to compile src/cpu/o3/alpha/thread_context.hh: no need for my name on this file src/cpu/o3/bpred_unit_impl.hh: Update RAS appropriately for MIPS src/cpu/o3/comm.hh: add some extra communication variables to aid in handling the delay slots src/cpu/o3/commit.hh: minor name fix for nextNPC functions. src/cpu/o3/commit_impl.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/rename_impl.hh: Fix necessary variables and functions for squashes with delay slots src/cpu/o3/cpu.cc: Update function interface ... adjust removeInstsNotInROB function to recognize delay slots insts src/cpu/o3/cpu.hh: update removeInstsNotInROB src/cpu/o3/decode.hh: declare necessary variables for handling delay slot src/cpu/o3/dyn_inst.hh: Add in MipsDynInst src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/rename.hh: declare necessary variables and adjust functions for handling delay slot src/cpu/o3/inst_queue.hh: src/cpu/simple/base.cc: no need for my name here src/cpu/o3/isa_specific.hh: add in MIPS files src/cpu/o3/scoreboard.hh: dont include alpha specific isa traits! src/cpu/o3/thread_context.hh: no need for my name here, i just rearranged where the file goes src/cpu/static_inst.hh: add isCondDelaySlot function src/cpu/o3/mips/cpu.cc: src/cpu/o3/mips/cpu.hh: src/cpu/o3/mips/cpu_builder.cc: src/cpu/o3/mips/cpu_impl.hh: src/cpu/o3/mips/dyn_inst.cc: src/cpu/o3/mips/dyn_inst.hh: src/cpu/o3/mips/dyn_inst_impl.hh: src/cpu/o3/mips/impl.hh: src/cpu/o3/mips/params.hh: src/cpu/o3/mips/thread_context.cc: src/cpu/o3/mips/thread_context.hh: MIPS file for O3CPU...mirrors ALPHA definition --HG-- extra : convert_revision : 9bb199b4085903e49ffd5a4c8ac44d11460d988c
153 lines
5.3 KiB
C++
Executable file
153 lines
5.3 KiB
C++
Executable file
/*
|
|
* Copyright (c) 2006 The Regents of The University of Michigan
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are
|
|
* met: redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer;
|
|
* redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution;
|
|
* neither the name of the copyright holders nor the names of its
|
|
* contributors may be used to endorse or promote products derived from
|
|
* this software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*
|
|
* Authors: Kevin Lim
|
|
* Korey Sewell
|
|
*/
|
|
|
|
#ifndef __CPU_O3_MIPS_CPU_HH__
|
|
#define __CPU_O3_MIPS_CPU_HH__
|
|
|
|
#include "arch/isa_traits.hh"
|
|
#include "cpu/thread_context.hh"
|
|
#include "cpu/o3/cpu.hh"
|
|
#include "sim/byteswap.hh"
|
|
|
|
class EndQuiesceEvent;
|
|
namespace Kernel {
|
|
class Statistics;
|
|
};
|
|
|
|
class TranslatingPort;
|
|
|
|
/**
|
|
* MipsO3CPU class. Derives from the FullO3CPU class, and
|
|
* implements all ISA and implementation specific functions of the
|
|
* CPU. This is the CPU class that is used for the SimObjects, and is
|
|
* what is given to the DynInsts. Most of its state exists in the
|
|
* FullO3CPU; the state is has is mainly for ISA specific
|
|
* functionality.
|
|
*/
|
|
template <class Impl>
|
|
class MipsO3CPU : public FullO3CPU<Impl>
|
|
{
|
|
protected:
|
|
typedef TheISA::IntReg IntReg;
|
|
typedef TheISA::FloatReg FloatReg;
|
|
typedef TheISA::FloatRegBits FloatRegBits;
|
|
typedef TheISA::MiscReg MiscReg;
|
|
typedef TheISA::RegFile RegFile;
|
|
typedef TheISA::MiscRegFile MiscRegFile;
|
|
|
|
public:
|
|
typedef O3ThreadState<Impl> ImplState;
|
|
typedef O3ThreadState<Impl> Thread;
|
|
typedef typename Impl::Params Params;
|
|
|
|
/** Constructs an MipsO3CPU with the given parameters. */
|
|
MipsO3CPU(Params *params);
|
|
|
|
/** Registers statistics. */
|
|
void regStats();
|
|
|
|
/** Translates instruction requestion in syscall emulation mode. */
|
|
Fault translateInstReq(RequestPtr &req, Thread *thread)
|
|
{
|
|
return thread->getProcessPtr()->pTable->translate(req);
|
|
}
|
|
|
|
/** Translates data read request in syscall emulation mode. */
|
|
Fault translateDataReadReq(RequestPtr &req, Thread *thread)
|
|
{
|
|
return thread->getProcessPtr()->pTable->translate(req);
|
|
}
|
|
|
|
/** Translates data write request in syscall emulation mode. */
|
|
Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
|
|
{
|
|
return thread->getProcessPtr()->pTable->translate(req);
|
|
}
|
|
|
|
/** Reads a miscellaneous register. */
|
|
MiscReg readMiscReg(int misc_reg, unsigned tid);
|
|
|
|
/** Reads a misc. register, including any side effects the read
|
|
* might have as defined by the architecture.
|
|
*/
|
|
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid);
|
|
|
|
/** Sets a miscellaneous register. */
|
|
Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
|
|
|
|
/** Sets a misc. register, including any side effects the write
|
|
* might have as defined by the architecture.
|
|
*/
|
|
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid);
|
|
|
|
/** Initiates a squash of all in-flight instructions for a given
|
|
* thread. The source of the squash is an external update of
|
|
* state through the TC.
|
|
*/
|
|
void squashFromTC(unsigned tid);
|
|
|
|
/** Traps to handle given fault. */
|
|
void trap(Fault fault, unsigned tid);
|
|
|
|
/** Executes a syscall.
|
|
* @todo: Determine if this needs to be virtual.
|
|
*/
|
|
void syscall(int64_t callnum, int tid);
|
|
/** Gets a syscall argument. */
|
|
IntReg getSyscallArg(int i, int tid);
|
|
|
|
/** Used to shift args for indirect syscall. */
|
|
void setSyscallArg(int i, IntReg val, int tid);
|
|
|
|
/** Sets the return value of a syscall. */
|
|
void setSyscallReturn(SyscallReturn return_value, int tid);
|
|
|
|
/** CPU read function, forwards read to LSQ. */
|
|
template <class T>
|
|
Fault read(RequestPtr &req, T &data, int load_idx)
|
|
{
|
|
return this->iew.ldstQueue.read(req, data, load_idx);
|
|
}
|
|
|
|
/** CPU write function, forwards write to LSQ. */
|
|
template <class T>
|
|
Fault write(RequestPtr &req, T &data, int store_idx)
|
|
{
|
|
return this->iew.ldstQueue.write(req, data, store_idx);
|
|
}
|
|
|
|
Addr lockAddr;
|
|
|
|
/** Temporary fix for the lock flag, works in the UP case. */
|
|
bool lockFlag;
|
|
};
|
|
|
|
#endif // __CPU_O3_MIPS_CPU_HH__
|