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succesfully but there are some minor quirks to iron out. Who would've known a DELAY SLOT introduces that much complexity?! arrgh! Anyways, a lot of this stuff had to do with my project at MIPS and me needing to know how I was going to get this working for the MIPS ISA. So I figured I would try to touch it up and throw it in here (I hate to introduce non-completely working components... ) src/arch/alpha/isa/mem.isa: spacing src/arch/mips/faults.cc: src/arch/mips/faults.hh: Gabe really authored this src/arch/mips/isa/decoder.isa: add StoreConditional Flag to instruction src/arch/mips/isa/formats/basic.isa: Steven really did this file src/arch/mips/isa/formats/branch.isa: fix bug for uncond/cond control src/arch/mips/isa/formats/mem.isa: Adjust O3CPU memory access to use new memory model interface. src/arch/mips/isa/formats/util.isa: update LoadStoreBase template src/arch/mips/isa_traits.cc: update SERIALIZE partially src/arch/mips/process.cc: src/arch/mips/process.hh: no need for this for NOW. ASID/Virtual addressing handles it src/arch/mips/regfile/misc_regfile.hh: add in clear() function and comments for future usage of special misc. regs src/cpu/base_dyn_inst.hh: add in nextNPC variable and supporting functions. add isCondDelaySlot function Update predTaken and mispredicted functions src/cpu/base_dyn_inst_impl.hh: init nextNPC src/cpu/o3/SConscript: add MIPS files to compile src/cpu/o3/alpha/thread_context.hh: no need for my name on this file src/cpu/o3/bpred_unit_impl.hh: Update RAS appropriately for MIPS src/cpu/o3/comm.hh: add some extra communication variables to aid in handling the delay slots src/cpu/o3/commit.hh: minor name fix for nextNPC functions. src/cpu/o3/commit_impl.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/rename_impl.hh: Fix necessary variables and functions for squashes with delay slots src/cpu/o3/cpu.cc: Update function interface ... adjust removeInstsNotInROB function to recognize delay slots insts src/cpu/o3/cpu.hh: update removeInstsNotInROB src/cpu/o3/decode.hh: declare necessary variables for handling delay slot src/cpu/o3/dyn_inst.hh: Add in MipsDynInst src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/rename.hh: declare necessary variables and adjust functions for handling delay slot src/cpu/o3/inst_queue.hh: src/cpu/simple/base.cc: no need for my name here src/cpu/o3/isa_specific.hh: add in MIPS files src/cpu/o3/scoreboard.hh: dont include alpha specific isa traits! src/cpu/o3/thread_context.hh: no need for my name here, i just rearranged where the file goes src/cpu/static_inst.hh: add isCondDelaySlot function src/cpu/o3/mips/cpu.cc: src/cpu/o3/mips/cpu.hh: src/cpu/o3/mips/cpu_builder.cc: src/cpu/o3/mips/cpu_impl.hh: src/cpu/o3/mips/dyn_inst.cc: src/cpu/o3/mips/dyn_inst.hh: src/cpu/o3/mips/dyn_inst_impl.hh: src/cpu/o3/mips/impl.hh: src/cpu/o3/mips/params.hh: src/cpu/o3/mips/thread_context.cc: src/cpu/o3/mips/thread_context.hh: MIPS file for O3CPU...mirrors ALPHA definition --HG-- extra : convert_revision : 9bb199b4085903e49ffd5a4c8ac44d11460d988c
203 lines
6 KiB
C++
203 lines
6 KiB
C++
/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_O3_COMM_HH__
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#define __CPU_O3_COMM_HH__
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#include <vector>
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#include "arch/faults.hh"
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#include "arch/isa_traits.hh"
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#include "cpu/inst_seq.hh"
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#include "sim/host.hh"
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// Typedef for physical register index type. Although the Impl would be the
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// most likely location for this, there are a few classes that need this
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// typedef yet are not templated on the Impl. For now it will be defined here.
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typedef short int PhysRegIndex;
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/** Struct that defines the information passed from fetch to decode. */
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template<class Impl>
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struct DefaultFetchDefaultDecode {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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Fault fetchFault;
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InstSeqNum fetchFaultSN;
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bool clearFetchFault;
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};
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/** Struct that defines the information passed from decode to rename. */
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template<class Impl>
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struct DefaultDecodeDefaultRename {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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};
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/** Struct that defines the information passed from rename to IEW. */
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template<class Impl>
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struct DefaultRenameDefaultIEW {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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};
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/** Struct that defines the information passed from IEW to commit. */
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template<class Impl>
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struct DefaultIEWDefaultCommit {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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bool squash[Impl::MaxThreads];
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bool branchMispredict[Impl::MaxThreads];
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bool branchTaken[Impl::MaxThreads];
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bool condDelaySlotBranch[Impl::MaxThreads];
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uint64_t mispredPC[Impl::MaxThreads];
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uint64_t nextPC[Impl::MaxThreads];
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InstSeqNum squashedSeqNum[Impl::MaxThreads];
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bool includeSquashInst[Impl::MaxThreads];
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};
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template<class Impl>
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struct IssueStruct {
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typedef typename Impl::DynInstPtr DynInstPtr;
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int size;
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DynInstPtr insts[Impl::MaxWidth];
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};
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/** Struct that defines all backwards communication. */
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template<class Impl>
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struct TimeBufStruct {
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struct decodeComm {
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bool squash;
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bool predIncorrect;
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uint64_t branchAddr;
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InstSeqNum doneSeqNum;
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InstSeqNum bdelayDoneSeqNum;
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// @todo: Might want to package this kind of branch stuff into a single
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// struct as it is used pretty frequently.
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bool branchMispredict;
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bool branchTaken;
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uint64_t mispredPC;
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uint64_t nextPC;
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unsigned branchCount;
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};
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decodeComm decodeInfo[Impl::MaxThreads];
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struct renameComm {
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};
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renameComm renameInfo[Impl::MaxThreads];
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struct iewComm {
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// Also eventually include skid buffer space.
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bool usedIQ;
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unsigned freeIQEntries;
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bool usedLSQ;
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unsigned freeLSQEntries;
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unsigned iqCount;
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unsigned ldstqCount;
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unsigned dispatched;
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unsigned dispatchedToLSQ;
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};
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iewComm iewInfo[Impl::MaxThreads];
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struct commitComm {
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bool usedROB;
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unsigned freeROBEntries;
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bool emptyROB;
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bool squash;
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bool robSquashing;
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bool branchMispredict;
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bool branchTaken;
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uint64_t mispredPC;
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uint64_t nextPC;
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// Represents the instruction that has either been retired or
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// squashed. Similar to having a single bus that broadcasts the
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// retired or squashed sequence number.
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InstSeqNum doneSeqNum;
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InstSeqNum bdelayDoneSeqNum;
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bool squashDelaySlot;
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//Just in case we want to do a commit/squash on a cycle
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//(necessary for multiple ROBs?)
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bool commitInsts;
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InstSeqNum squashSeqNum;
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// Communication specifically to the IQ to tell the IQ that it can
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// schedule a non-speculative instruction.
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InstSeqNum nonSpecSeqNum;
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// Hack for now to send back an uncached access to the IEW stage.
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typedef typename Impl::DynInstPtr DynInstPtr;
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bool uncached;
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DynInstPtr uncachedLoad;
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bool interruptPending;
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bool clearInterrupt;
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};
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commitComm commitInfo[Impl::MaxThreads];
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bool decodeBlock[Impl::MaxThreads];
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bool decodeUnblock[Impl::MaxThreads];
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bool renameBlock[Impl::MaxThreads];
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bool renameUnblock[Impl::MaxThreads];
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bool iewBlock[Impl::MaxThreads];
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bool iewUnblock[Impl::MaxThreads];
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bool commitBlock[Impl::MaxThreads];
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bool commitUnblock[Impl::MaxThreads];
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};
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#endif //__CPU_O3_COMM_HH__
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