19a5b68db7
This patch makes it possible to once again build gem5 without any ISA. The main purpose is to enable work around the interconnect and memory system without having to build any CPU models or device models. The regress script is updated to include the NULL ISA target. Currently no regressions make use of it, but all the testers could (and perhaps should) transition to it. --HG-- rename : build_opts/NOISA => build_opts/NULL rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc
295 lines
7.7 KiB
C++
295 lines
7.7 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Sascha Bischoff
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*/
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// This file will contain default statistics for the simulator that
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// don't really belong to a specific simulator object
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#include <fstream>
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#include <iostream>
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#include <list>
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#include "base/callback.hh"
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#include "base/hostinfo.hh"
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#include "base/statistics.hh"
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#include "base/time.hh"
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#include "cpu/base.hh"
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#include "sim/eventq_impl.hh"
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#include "sim/stat_control.hh"
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using namespace std;
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Stats::Formula simSeconds;
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Stats::Value simTicks;
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Stats::Value finalTick;
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Stats::Value simFreq;
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namespace Stats {
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Time statTime(true);
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Tick startTick;
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Event *dumpEvent;
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struct SimTicksReset : public Callback
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{
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void process()
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{
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statTime.setTimer();
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startTick = curTick();
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}
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};
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double
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statElapsedTime()
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{
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Time now;
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now.setTimer();
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Time elapsed = now - statTime;
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return elapsed;
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}
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Tick
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statElapsedTicks()
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{
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return curTick() - startTick;
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}
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Tick
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statFinalTick()
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{
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return curTick();
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}
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SimTicksReset simTicksReset;
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struct Global
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{
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Stats::Formula hostInstRate;
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Stats::Formula hostOpRate;
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Stats::Formula hostTickRate;
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Stats::Value hostMemory;
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Stats::Value hostSeconds;
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Stats::Value simInsts;
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Stats::Value simOps;
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Global();
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};
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Global::Global()
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{
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simInsts
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.functor(BaseCPU::numSimulatedInsts)
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.name("sim_insts")
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.desc("Number of instructions simulated")
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.precision(0)
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.prereq(simInsts)
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;
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simOps
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.functor(BaseCPU::numSimulatedOps)
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.name("sim_ops")
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.desc("Number of ops (including micro ops) simulated")
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.precision(0)
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.prereq(simOps)
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;
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simSeconds
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.name("sim_seconds")
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.desc("Number of seconds simulated")
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;
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simFreq
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.scalar(SimClock::Frequency)
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.name("sim_freq")
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.desc("Frequency of simulated ticks")
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;
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simTicks
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.functor(statElapsedTicks)
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.name("sim_ticks")
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.desc("Number of ticks simulated")
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;
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finalTick
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.functor(statFinalTick)
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.name("final_tick")
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.desc("Number of ticks from beginning of simulation \
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(restored from checkpoints and never reset)")
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;
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hostInstRate
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.name("host_inst_rate")
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.desc("Simulator instruction rate (inst/s)")
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.precision(0)
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.prereq(simInsts)
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;
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hostOpRate
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.name("host_op_rate")
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.desc("Simulator op (including micro ops) rate (op/s)")
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.precision(0)
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.prereq(simOps)
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;
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hostMemory
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.functor(memUsage)
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.name("host_mem_usage")
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.desc("Number of bytes of host memory used")
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.prereq(hostMemory)
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;
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hostSeconds
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.functor(statElapsedTime)
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.name("host_seconds")
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.desc("Real time elapsed on the host")
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.precision(2)
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;
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hostTickRate
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.name("host_tick_rate")
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.desc("Simulator tick rate (ticks/s)")
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.precision(0)
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;
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simSeconds = simTicks / simFreq;
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hostInstRate = simInsts / hostSeconds;
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hostOpRate = simOps / hostSeconds;
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hostTickRate = simTicks / hostSeconds;
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registerResetCallback(&simTicksReset);
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}
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void
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initSimStats()
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{
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static Global global;
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}
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/**
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* Event to dump and/or reset the statistics.
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*/
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class StatEvent : public Event
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{
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private:
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bool dump;
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bool reset;
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Tick repeat;
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public:
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StatEvent(bool _dump, bool _reset, Tick _repeat)
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: Event(Stat_Event_Pri, AutoDelete),
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dump(_dump), reset(_reset), repeat(_repeat)
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{
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}
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virtual void
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process()
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{
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if (dump)
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Stats::dump();
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if (reset)
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Stats::reset();
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if (repeat) {
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Stats::schedStatEvent(dump, reset, curTick() + repeat, repeat);
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}
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}
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};
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void
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schedStatEvent(bool dump, bool reset, Tick when, Tick repeat)
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{
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dumpEvent = new StatEvent(dump, reset, repeat);
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mainEventQueue.schedule(dumpEvent, when);
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}
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void
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periodicStatDump(Tick period)
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{
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/*
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* If the period is set to 0, then we do not want to dump periodically,
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* thus we deschedule the event. Else, if the period is not 0, but the event
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* has already been scheduled, we need to get rid of the old event before we
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* create a new one, as the old event will no longer be moved forward in the
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* event that we resume from a checkpoint.
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*/
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if (dumpEvent != NULL && (period == 0 || dumpEvent->scheduled())) {
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// Event should AutoDelete, so we do not need to free it.
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mainEventQueue.deschedule(dumpEvent);
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}
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/*
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* If the period is not 0, we schedule the event. If this is called with a
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* period that is less than the current tick, then we shift the first dump
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* by curTick. This ensures that we do not schedule the event is the past.
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*/
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if (period != 0) {
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// Schedule the event
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if (period >= curTick()) {
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schedStatEvent(true, true, (Tick)period, (Tick)period);
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} else {
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schedStatEvent(true, true, (Tick)period + curTick(), (Tick)period);
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}
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}
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}
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void
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updateEvents()
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{
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/*
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* If the dumpEvent has been scheduled, but is scheduled in the past, then
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* we need to shift the event to be at a valid point in time. Therefore, we
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* shift the event by curTick.
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*/
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if (dumpEvent != NULL &&
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(dumpEvent->scheduled() && dumpEvent->when() < curTick())) {
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// shift by curTick() and reschedule
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Tick _when = dumpEvent->when();
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mainEventQueue.reschedule(dumpEvent, _when + curTick());
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}
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}
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} // namespace Stats
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