Andreas Hansson 19a5b68db7 arch: Resurrect the NOISA build target and rename it NULL ... This patch makes it possible to once again build gem5 without any ISA. The main purpose is to enable work around the interconnect and memory system without having to build any CPU models or device models. The regress script is updated to include the NULL ISA target. Currently no regressions make use of it, but all the testers could (and perhaps should) transition to it. --HG-- rename : build_opts/NOISA => build_opts/NULL rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc		2013-09-04 13:22:57 -04:00
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base.cc	arch: Resurrect the NOISA build target and rename it NULL	2013-09-04 13:22:57 -04:00
base.hh	mem: Reorganize cache tags and make them a SimObject	2013-06-27 05:49:50 -04:00
cacheset.hh	mem: Reorganize cache tags and make them a SimObject	2013-06-27 05:49:50 -04:00
fa_lru.cc	mem: Reorganize cache tags and make them a SimObject	2013-06-27 05:49:50 -04:00
fa_lru.hh	mem: Reorganize cache tags and make them a SimObject	2013-06-27 05:49:50 -04:00
lru.cc	mem: Reorganize cache tags and make them a SimObject	2013-06-27 05:49:50 -04:00
lru.hh	mem: Reorganize cache tags and make them a SimObject	2013-06-27 05:49:50 -04:00
SConscript	arch: Resurrect the NOISA build target and rename it NULL	2013-09-04 13:22:57 -04:00
Tags.py	mem: Set the cache line size on a system level	2013-07-18 08:31:16 -04:00