bb80f71f21
SConscript:
comment out most devices
add vport.cc
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
push in alpha name space
fix for new memory system
arch/alpha/faults.cc:
arch/alpha/faults.hh:
Added an unimplemented fault that can be returned if a certain
function isn't implemented
arch/alpha/freebsd/system.cc:
arch/alpha/linux/system.cc:
arch/alpha/stacktrace.cc:
arch/alpha/system.cc:
arch/alpha/tlb.hh:
arch/alpha/tru64/system.cc:
fixed for new memory system
arch/alpha/tlb.cc:
fixed for new memory system
removed code that seems to have no purpose
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
fixed for new memory system
put in namespace AlphaISA
base/remote_gdb.cc:
fix for new memory system
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
create two ports one of physical accesses and one for superpage accesses
Add functions getVirtPort() getPhysPort() delVirtPort(). To get statically
allocated physical or virtual ports or if an execcontext is passed in
get a dynamically allocated virtual port
dev/alpha_console.cc:
dev/alpha_console.hh:
Redo for new memory system
dev/io_device.cc:
dev/io_device.hh:
new I/O devices for new memory system
kern/linux/events.cc:
kern/linux/printk.cc:
kern/linux/printk.hh:
kern/tru64/dump_mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
Arguments now in namespaces
kern/tru64/tru64_events.cc:
mem/bus.cc:
fix for new memory syste
mem/physical.hh:
new addressranges function
getPort should be public
mem/port.hh:
Add write/read methods to functional port
update getDeviceAddrRanges to have a list of both snoops and response lists
sim/pseudo_inst.cc:
sim/system.cc:
sim/system.hh:
Update for new mem system
sim/vptr.hh:
comment out code and replace with panics
This will need to be fixed at some point, but it's not easy.
--HG--
extra : convert_revision : 41f41f422cfbab3751284d55cccb6ea64a7956e2
187 lines
6.1 KiB
C++
187 lines
6.1 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/alpha/faults.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/base.hh"
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#include "base/trace.hh"
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#if FULL_SYSTEM
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#include "arch/alpha/ev5.hh"
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#endif
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namespace AlphaISA
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{
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FaultName MachineCheckFault::_name = "mchk";
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FaultVect MachineCheckFault::_vect = 0x0401;
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FaultStat MachineCheckFault::_count;
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FaultName AlignmentFault::_name = "unalign";
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FaultVect AlignmentFault::_vect = 0x0301;
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FaultStat AlignmentFault::_count;
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FaultName ResetFault::_name = "reset";
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FaultVect ResetFault::_vect = 0x0001;
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FaultStat ResetFault::_count;
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FaultName ArithmeticFault::_name = "arith";
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FaultVect ArithmeticFault::_vect = 0x0501;
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FaultStat ArithmeticFault::_count;
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FaultName InterruptFault::_name = "interrupt";
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FaultVect InterruptFault::_vect = 0x0101;
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FaultStat InterruptFault::_count;
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FaultName NDtbMissFault::_name = "dtb_miss_single";
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FaultVect NDtbMissFault::_vect = 0x0201;
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FaultStat NDtbMissFault::_count;
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FaultName PDtbMissFault::_name = "dtb_miss_double";
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FaultVect PDtbMissFault::_vect = 0x0281;
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FaultStat PDtbMissFault::_count;
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FaultName DtbPageFault::_name = "dfault";
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FaultVect DtbPageFault::_vect = 0x0381;
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FaultStat DtbPageFault::_count;
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FaultName DtbAcvFault::_name = "dfault";
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FaultVect DtbAcvFault::_vect = 0x0381;
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FaultStat DtbAcvFault::_count;
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FaultName DtbAlignmentFault::_name = "unalign";
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FaultVect DtbAlignmentFault::_vect = 0x0301;
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FaultStat DtbAlignmentFault::_count;
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FaultName ItbMissFault::_name = "itbmiss";
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FaultVect ItbMissFault::_vect = 0x0181;
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FaultStat ItbMissFault::_count;
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FaultName ItbPageFault::_name = "itbmiss";
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FaultVect ItbPageFault::_vect = 0x0181;
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FaultStat ItbPageFault::_count;
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FaultName ItbAcvFault::_name = "iaccvio";
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FaultVect ItbAcvFault::_vect = 0x0081;
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FaultStat ItbAcvFault::_count;
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FaultName UnimplementedOpcodeFault::_name = "opdec";
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FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
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FaultStat UnimplementedOpcodeFault::_count;
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FaultName FloatEnableFault::_name = "fen";
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FaultVect FloatEnableFault::_vect = 0x0581;
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FaultStat FloatEnableFault::_count;
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FaultName PalFault::_name = "pal";
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FaultVect PalFault::_vect = 0x2001;
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FaultStat PalFault::_count;
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FaultName IntegerOverflowFault::_name = "intover";
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FaultVect IntegerOverflowFault::_vect = 0x0501;
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FaultStat IntegerOverflowFault::_count;
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FaultName UnimpFault::_name = "Unimplemented Simulator feature";
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FaultVect UnimpFault::_vect = 0x0001;
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FaultStat UnimpFault::_count;
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#if FULL_SYSTEM
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void AlphaFault::invoke(ExecContext * xc)
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{
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FaultBase::invoke(xc);
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countStat()++;
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// exception restart address
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if (setRestartAddress() || !xc->inPalMode())
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xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->readPC());
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if (skipFaultingInstruction()) {
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// traps... skip faulting instruction.
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xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
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xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
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}
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xc->setPC(xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
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xc->setNextPC(xc->readPC() + sizeof(MachInst));
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}
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void ArithmeticFault::invoke(ExecContext * xc)
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{
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FaultBase::invoke(xc);
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panic("Arithmetic traps are unimplemented!");
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}
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void DtbFault::invoke(ExecContext * xc)
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{
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// Set fault address and flags. Even though we're modeling an
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// EV5, we use the EV6 technique of not latching fault registers
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// on VPTE loads (instead of locking the registers until IPR_VA is
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// read, like the EV5). The EV6 approach is cleaner and seems to
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// work with EV5 PAL code, but not the other way around.
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if (!xc->misspeculating()
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&& !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
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// set VA register with faulting address
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xc->setMiscReg(AlphaISA::IPR_VA, vaddr);
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// set MM_STAT register flags
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xc->setMiscReg(AlphaISA::IPR_MM_STAT,
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(((EV5::Opcode(xc->getInst()) & 0x3f) << 11)
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| ((EV5::Ra(xc->getInst()) & 0x1f) << 6)
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| (flags & 0x3f)));
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// set VA_FORM register with faulting formatted address
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xc->setMiscReg(AlphaISA::IPR_VA_FORM,
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xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
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}
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AlphaFault::invoke(xc);
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}
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void ItbFault::invoke(ExecContext * xc)
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{
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if (!xc->misspeculating()) {
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xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
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xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
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xc->readMiscReg(AlphaISA::IPR_IVPTBR) |
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(AlphaISA::VAddr(pc).vpn() << 3));
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}
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AlphaFault::invoke(xc);
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}
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void UnimpFault::invoke(ExecContext * xc)
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{
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FaultBase::invoke(xc);
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panic("Unimpfault: %s\n", panicStr.c_str());
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}
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#endif
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} // namespace AlphaISA
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