19273164da
--HG-- rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr => tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout => tests/long/00.gzip/ref/sparc/linux/o3-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr => tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout => tests/long/00.gzip/ref/sparc/linux/simple-timing/simout rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr => tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout => tests/long/00.gzip/ref/x86/linux/simple-atomic/simout rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stderr => tests/long/00.gzip/ref/x86/linux/simple-timing/simerr rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stdout => tests/long/00.gzip/ref/x86/linux/simple-timing/simout rename : tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr => tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout => tests/long/10.mcf/ref/sparc/linux/simple-timing/simout rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr => tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout => tests/long/10.mcf/ref/x86/linux/simple-atomic/simout rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stderr => tests/long/10.mcf/ref/x86/linux/simple-timing/simerr rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stdout => tests/long/10.mcf/ref/x86/linux/simple-timing/simout rename : tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stderr => tests/long/20.parser/ref/x86/linux/simple-atomic/simerr rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stdout => tests/long/20.parser/ref/x86/linux/simple-atomic/simout rename : tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/20.parser/ref/x86/linux/simple-timing/stderr => tests/long/20.parser/ref/x86/linux/simple-timing/simerr rename : tests/long/20.parser/ref/x86/linux/simple-timing/stdout => tests/long/20.parser/ref/x86/linux/simple-timing/simout rename : tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr => tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout => tests/long/30.eon/ref/alpha/tru64/o3-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr => tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout => tests/long/30.eon/ref/alpha/tru64/simple-timing/simout rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr => tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout => tests/long/50.vortex/ref/sparc/linux/simple-timing/simout rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr => tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout => tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stderr => tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stdout => tests/long/60.bzip2/ref/x86/linux/simple-timing/simout rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/m5stats.txt => tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr => tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout => tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr => tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout => tests/long/70.twolf/ref/sparc/linux/simple-timing/simout rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr => tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout => tests/long/70.twolf/ref/x86/linux/simple-atomic/simout rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stderr => tests/long/70.twolf/ref/x86/linux/simple-timing/simerr rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stdout => tests/long/70.twolf/ref/x86/linux/simple-timing/simout rename : tests/long/70.twolf/ref/x86/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr => tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout => tests/quick/00.hello/ref/alpha/linux/o3-timing/simout rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr => tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout => tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr => tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout => tests/quick/00.hello/ref/alpha/linux/simple-timing/simout rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout => tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr => tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout => tests/quick/00.hello/ref/mips/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stderr => tests/quick/00.hello/ref/mips/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stdout => tests/quick/00.hello/ref/mips/linux/simple-timing/simout rename : tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr => tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout => tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr => tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout => tests/quick/00.hello/ref/sparc/linux/simple-timing/simout rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr => tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout => tests/quick/00.hello/ref/x86/linux/simple-atomic/simout rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stderr => tests/quick/00.hello/ref/x86/linux/simple-timing/simerr rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stdout => tests/quick/00.hello/ref/x86/linux/simple-timing/simout rename : tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout => tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr => tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout => tests/quick/20.eio-short/ref/alpha/eio/detailed/simout rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stderr => tests/quick/50.memtest/ref/alpha/linux/memtest/simerr rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stdout => tests/quick/50.memtest/ref/alpha/linux/memtest/simout rename : tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt => tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
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736 lines
82 KiB
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1388930 # Simulator instruction rate (inst/s)
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host_mem_usage 287800 # Number of bytes of host memory used
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host_seconds 42.75 # Real time elapsed on the host
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host_tick_rate 46129218174 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 59379829 # Number of instructions simulated
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sim_seconds 1.972135 # Number of seconds simulated
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sim_ticks 1972135479000 # Number of ticks simulated
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system.cpu0.dcache.LoadLockedReq_accesses 192618 # number of LoadLockedReq accesses(hits+misses)
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system.cpu0.dcache.LoadLockedReq_avg_miss_latency 14266.203842 # average LoadLockedReq miss latency
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system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11266.203842 # average LoadLockedReq mshr miss latency
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system.cpu0.dcache.LoadLockedReq_hits 175909 # number of LoadLockedReq hits
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system.cpu0.dcache.LoadLockedReq_miss_latency 238374000 # number of LoadLockedReq miss cycles
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system.cpu0.dcache.LoadLockedReq_miss_rate 0.086747 # miss rate for LoadLockedReq accesses
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system.cpu0.dcache.LoadLockedReq_misses 16709 # number of LoadLockedReq misses
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system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 188247000 # number of LoadLockedReq MSHR miss cycles
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system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.086747 # mshr miss rate for LoadLockedReq accesses
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system.cpu0.dcache.LoadLockedReq_mshr_misses 16709 # number of LoadLockedReq MSHR misses
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system.cpu0.dcache.ReadReq_accesses 8482392 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_avg_miss_latency 25694.187455 # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.147984 # average ReadReq mshr miss latency
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system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.cpu0.dcache.ReadReq_hits 7443656 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_miss_latency 26689477500 # number of ReadReq miss cycles
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system.cpu0.dcache.ReadReq_miss_rate 0.122458 # miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_misses 1038736 # number of ReadReq misses
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system.cpu0.dcache.ReadReq_mshr_miss_latency 23573228500 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_rate 0.122458 # mshr miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_mshr_misses 1038736 # number of ReadReq MSHR misses
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system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 868701000 # number of ReadReq MSHR uncacheable cycles
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system.cpu0.dcache.StoreCondReq_accesses 191654 # number of StoreCondReq accesses(hits+misses)
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system.cpu0.dcache.StoreCondReq_avg_miss_latency 55352.322833 # average StoreCondReq miss latency
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system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52352.322833 # average StoreCondReq mshr miss latency
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system.cpu0.dcache.StoreCondReq_hits 163305 # number of StoreCondReq hits
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system.cpu0.dcache.StoreCondReq_miss_latency 1569183000 # number of StoreCondReq miss cycles
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system.cpu0.dcache.StoreCondReq_miss_rate 0.147918 # miss rate for StoreCondReq accesses
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system.cpu0.dcache.StoreCondReq_misses 28349 # number of StoreCondReq misses
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system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1484136000 # number of StoreCondReq MSHR miss cycles
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system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.147918 # mshr miss rate for StoreCondReq accesses
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system.cpu0.dcache.StoreCondReq_mshr_misses 28349 # number of StoreCondReq MSHR misses
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system.cpu0.dcache.WriteReq_accesses 5845269 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_avg_miss_latency 55891.595936 # average WriteReq miss latency
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system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.595936 # average WriteReq mshr miss latency
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system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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system.cpu0.dcache.WriteReq_hits 5466012 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_miss_latency 21197279000 # number of WriteReq miss cycles
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system.cpu0.dcache.WriteReq_miss_rate 0.064883 # miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_misses 379257 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_mshr_miss_latency 20059508000 # number of WriteReq MSHR miss cycles
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system.cpu0.dcache.WriteReq_mshr_miss_rate 0.064883 # mshr miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_mshr_misses 379257 # number of WriteReq MSHR misses
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system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1225890000 # number of WriteReq MSHR uncacheable cycles
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system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu0.dcache.avg_refs 9.984583 # Average number of references to valid blocks.
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system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.demand_accesses 14327661 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_avg_miss_latency 33770.798939 # average overall miss latency
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system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency
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system.cpu0.dcache.demand_hits 12909668 # number of demand (read+write) hits
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system.cpu0.dcache.demand_miss_latency 47886756500 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_miss_rate 0.098969 # miss rate for demand accesses
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system.cpu0.dcache.demand_misses 1417993 # number of demand (read+write) misses
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system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu0.dcache.demand_mshr_miss_latency 43632736500 # number of demand (read+write) MSHR miss cycles
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system.cpu0.dcache.demand_mshr_miss_rate 0.098969 # mshr miss rate for demand accesses
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system.cpu0.dcache.demand_mshr_misses 1417993 # number of demand (read+write) MSHR misses
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.overall_accesses 14327661 # number of overall (read+write) accesses
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system.cpu0.dcache.overall_avg_miss_latency 33770.798939 # average overall miss latency
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system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.770025 # average overall mshr miss latency
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system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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system.cpu0.dcache.overall_hits 12909668 # number of overall hits
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system.cpu0.dcache.overall_miss_latency 47886756500 # number of overall miss cycles
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system.cpu0.dcache.overall_miss_rate 0.098969 # miss rate for overall accesses
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system.cpu0.dcache.overall_misses 1417993 # number of overall misses
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system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu0.dcache.overall_mshr_miss_latency 43632736500 # number of overall MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_rate 0.098969 # mshr miss rate for overall accesses
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system.cpu0.dcache.overall_mshr_misses 1417993 # number of overall MSHR misses
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system.cpu0.dcache.overall_mshr_uncacheable_latency 2094591000 # number of overall MSHR uncacheable cycles
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system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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|
system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu0.dcache.replacements 1338626 # number of replacements
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|
system.cpu0.dcache.sampled_refs 1339138 # Sample count of references to valid blocks.
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system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu0.dcache.tagsinuse 503.746259 # Cycle average of tags in use
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system.cpu0.dcache.total_refs 13370734 # Total number of references to valid blocks.
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system.cpu0.dcache.warmup_cycle 84055000 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.writebacks 403562 # number of writebacks
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system.cpu0.dtb.accesses 719860 # DTB accesses
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system.cpu0.dtb.acv 289 # DTB access violations
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system.cpu0.dtb.hits 14696400 # DTB hits
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system.cpu0.dtb.misses 8485 # DTB misses
|
|
system.cpu0.dtb.read_accesses 524201 # DTB read accesses
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system.cpu0.dtb.read_acv 174 # DTB read access violations
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|
system.cpu0.dtb.read_hits 8658591 # DTB read hits
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system.cpu0.dtb.read_misses 7687 # DTB read misses
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system.cpu0.dtb.write_accesses 195659 # DTB write accesses
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|
system.cpu0.dtb.write_acv 115 # DTB write access violations
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system.cpu0.dtb.write_hits 6037809 # DTB write hits
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system.cpu0.dtb.write_misses 798 # DTB write misses
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system.cpu0.icache.ReadReq_accesses 54124252 # number of ReadReq accesses(hits+misses)
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system.cpu0.icache.ReadReq_avg_miss_latency 14681.475669 # average ReadReq miss latency
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|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.724759 # average ReadReq mshr miss latency
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system.cpu0.icache.ReadReq_hits 53208030 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_miss_latency 13451491000 # number of ReadReq miss cycles
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|
system.cpu0.icache.ReadReq_miss_rate 0.016928 # miss rate for ReadReq accesses
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|
system.cpu0.icache.ReadReq_misses 916222 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency 10702137000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate 0.016928 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_misses 916222 # number of ReadReq MSHR misses
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|
system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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|
system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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|
system.cpu0.icache.avg_refs 58.081472 # Average number of references to valid blocks.
|
|
system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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|
system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked
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|
system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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|
system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.demand_accesses 54124252 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_avg_miss_latency 14681.475669 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency
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|
system.cpu0.icache.demand_hits 53208030 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_miss_latency 13451491000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_rate 0.016928 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_misses 916222 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_miss_latency 10702137000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_rate 0.016928 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_misses 916222 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.overall_accesses 54124252 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_avg_miss_latency 14681.475669 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency 11680.724759 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_hits 53208030 # number of overall hits
|
|
system.cpu0.icache.overall_miss_latency 13451491000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_rate 0.016928 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_misses 916222 # number of overall misses
|
|
system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_miss_latency 10702137000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_rate 0.016928 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_misses 916222 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu0.icache.replacements 915582 # number of replacements
|
|
system.cpu0.icache.sampled_refs 916093 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu0.icache.tagsinuse 508.642784 # Cycle average of tags in use
|
|
system.cpu0.icache.total_refs 53208030 # Total number of references to valid blocks.
|
|
system.cpu0.icache.warmup_cycle 39455749000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.writebacks 0 # number of writebacks
|
|
system.cpu0.idle_fraction 0.933199 # Percentage of idle cycles
|
|
system.cpu0.itb.accesses 3953623 # ITB accesses
|
|
system.cpu0.itb.acv 143 # ITB acv
|
|
system.cpu0.itb.hits 3949782 # ITB hits
|
|
system.cpu0.itb.misses 3841 # ITB misses
|
|
system.cpu0.kern.callpal 187998 # number of callpals executed
|
|
system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu0.kern.callpal_wripir 91 0.05% 0.05% # number of callpals executed
|
|
system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed
|
|
system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed
|
|
system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed
|
|
system.cpu0.kern.callpal_swpctx 3868 2.06% 2.11% # number of callpals executed
|
|
system.cpu0.kern.callpal_tbi 44 0.02% 2.13% # number of callpals executed
|
|
system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed
|
|
system.cpu0.kern.callpal_swpipl 172054 91.52% 93.65% # number of callpals executed
|
|
system.cpu0.kern.callpal_rdps 6698 3.56% 97.22% # number of callpals executed
|
|
system.cpu0.kern.callpal_wrkgp 1 0.00% 97.22% # number of callpals executed
|
|
system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed
|
|
system.cpu0.kern.callpal_rdusp 7 0.00% 97.22% # number of callpals executed
|
|
system.cpu0.kern.callpal_whami 2 0.00% 97.22% # number of callpals executed
|
|
system.cpu0.kern.callpal_rti 4713 2.51% 99.73% # number of callpals executed
|
|
system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed
|
|
system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.hwrei 202882 # number of hwrei instructions executed
|
|
system.cpu0.kern.inst.quiesce 6254 # number of quiesce instructions executed
|
|
system.cpu0.kern.ipl_count 178892 # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count_0 72633 40.60% 40.60% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count_21 131 0.07% 40.67% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count_22 1987 1.11% 41.79% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count_30 6 0.00% 41.79% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count_31 104135 58.21% 100.00% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_good 144646 # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good_0 71264 49.27% 49.27% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good_22 1987 1.37% 50.73% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good_30 6 0.00% 50.74% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good_31 71258 49.26% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_ticks 1972134721000 # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks_0 1908424308500 96.77% 96.77% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks_21 96335500 0.00% 96.77% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks_22 576469500 0.03% 96.80% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks_30 5442500 0.00% 96.80% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks_31 63032165000 3.20% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_used_0 0.981152 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used_31 0.684285 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.mode_good_kernel 1232
|
|
system.cpu0.kern.mode_good_user 1233
|
|
system.cpu0.kern.mode_good_idle 0
|
|
system.cpu0.kern.mode_switch_kernel 7237 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch_user 1233 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good_kernel 0.170236 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_ticks_kernel 1968330428000 99.81% 99.81% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks_user 3804291000 0.19% 100.00% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode
|
|
system.cpu0.kern.swap_context 3869 # number of times the context was actually changed
|
|
system.cpu0.kern.syscall 224 # number of syscalls executed
|
|
system.cpu0.kern.syscall_2 6 2.68% 2.68% # number of syscalls executed
|
|
system.cpu0.kern.syscall_3 19 8.48% 11.16% # number of syscalls executed
|
|
system.cpu0.kern.syscall_4 3 1.34% 12.50% # number of syscalls executed
|
|
system.cpu0.kern.syscall_6 30 13.39% 25.89% # number of syscalls executed
|
|
system.cpu0.kern.syscall_12 1 0.45% 26.34% # number of syscalls executed
|
|
system.cpu0.kern.syscall_15 1 0.45% 26.79% # number of syscalls executed
|
|
system.cpu0.kern.syscall_17 10 4.46% 31.25% # number of syscalls executed
|
|
system.cpu0.kern.syscall_19 6 2.68% 33.93% # number of syscalls executed
|
|
system.cpu0.kern.syscall_20 4 1.79% 35.71% # number of syscalls executed
|
|
system.cpu0.kern.syscall_23 2 0.89% 36.61% # number of syscalls executed
|
|
system.cpu0.kern.syscall_24 4 1.79% 38.39% # number of syscalls executed
|
|
system.cpu0.kern.syscall_33 8 3.57% 41.96% # number of syscalls executed
|
|
system.cpu0.kern.syscall_41 2 0.89% 42.86% # number of syscalls executed
|
|
system.cpu0.kern.syscall_45 39 17.41% 60.27% # number of syscalls executed
|
|
system.cpu0.kern.syscall_47 4 1.79% 62.05% # number of syscalls executed
|
|
system.cpu0.kern.syscall_48 7 3.12% 65.18% # number of syscalls executed
|
|
system.cpu0.kern.syscall_54 9 4.02% 69.20% # number of syscalls executed
|
|
system.cpu0.kern.syscall_58 1 0.45% 69.64% # number of syscalls executed
|
|
system.cpu0.kern.syscall_59 5 2.23% 71.88% # number of syscalls executed
|
|
system.cpu0.kern.syscall_71 32 14.29% 86.16% # number of syscalls executed
|
|
system.cpu0.kern.syscall_73 3 1.34% 87.50% # number of syscalls executed
|
|
system.cpu0.kern.syscall_74 9 4.02% 91.52% # number of syscalls executed
|
|
system.cpu0.kern.syscall_87 1 0.45% 91.96% # number of syscalls executed
|
|
system.cpu0.kern.syscall_90 2 0.89% 92.86% # number of syscalls executed
|
|
system.cpu0.kern.syscall_92 7 3.12% 95.98% # number of syscalls executed
|
|
system.cpu0.kern.syscall_97 2 0.89% 96.87% # number of syscalls executed
|
|
system.cpu0.kern.syscall_98 2 0.89% 97.77% # number of syscalls executed
|
|
system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed
|
|
system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed
|
|
system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed
|
|
system.cpu0.not_idle_fraction 0.066801 # Percentage of non-idle cycles
|
|
system.cpu0.numCycles 3944270958 # number of cpu cycles simulated
|
|
system.cpu0.num_insts 54115477 # Number of instructions executed
|
|
system.cpu0.num_refs 14937789 # Number of memory references
|
|
system.cpu1.dcache.LoadLockedReq_accesses 12334 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency 13393.700787 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10393.700787 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_hits 11318 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency 13608000 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate 0.082374 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_misses 1016 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10560000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.082374 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses 1016 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_accesses 1020508 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency 15788.930188 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12788.832374 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.ReadReq_hits 984726 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_miss_latency 564959500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_rate 0.035063 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_misses 35782 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency 457610000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035063 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_misses 35782 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 12526000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.StoreCondReq_accesses 12269 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency 46915.603129 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43915.603129 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_hits 9840 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_miss_latency 113958000 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_rate 0.197979 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_misses 2429 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106671000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.197979 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses 2429 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_accesses 649988 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency 54642.103265 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51642.103265 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_hits 623648 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_miss_latency 1439273000 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_rate 0.040524 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_misses 26340 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency 1360253000 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040524 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_misses 26340 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303022000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_refs 30.126995 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.demand_accesses 1670496 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_avg_miss_latency 32262.845691 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_hits 1608374 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_miss_latency 2004232500 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_rate 0.037188 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_misses 62122 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_miss_latency 1817863000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_rate 0.037188 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_misses 62122 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.overall_accesses 1670496 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_avg_miss_latency 32262.845691 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency 29262.789350 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_hits 1608374 # number of overall hits
|
|
system.cpu1.dcache.overall_miss_latency 2004232500 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_rate 0.037188 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_misses 62122 # number of overall misses
|
|
system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_miss_latency 1817863000 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_rate 0.037188 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_misses 62122 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency 315548000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu1.dcache.replacements 53749 # number of replacements
|
|
system.cpu1.dcache.sampled_refs 54144 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu1.dcache.tagsinuse 388.873056 # Cycle average of tags in use
|
|
system.cpu1.dcache.total_refs 1631196 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.warmup_cycle 1954644714000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.writebacks 26833 # number of writebacks
|
|
system.cpu1.dtb.accesses 302878 # DTB accesses
|
|
system.cpu1.dtb.acv 84 # DTB access violations
|
|
system.cpu1.dtb.hits 1693796 # DTB hits
|
|
system.cpu1.dtb.misses 3106 # DTB misses
|
|
system.cpu1.dtb.read_accesses 205838 # DTB read accesses
|
|
system.cpu1.dtb.read_acv 36 # DTB read access violations
|
|
system.cpu1.dtb.read_hits 1029675 # DTB read hits
|
|
system.cpu1.dtb.read_misses 2750 # DTB read misses
|
|
system.cpu1.dtb.write_accesses 97040 # DTB write accesses
|
|
system.cpu1.dtb.write_acv 48 # DTB write access violations
|
|
system.cpu1.dtb.write_hits 664121 # DTB write hits
|
|
system.cpu1.dtb.write_misses 356 # DTB write misses
|
|
system.cpu1.icache.ReadReq_accesses 5267542 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_avg_miss_latency 14619.415532 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11618.958024 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_hits 5180112 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_miss_latency 1278175500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_rate 0.016598 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_misses 87430 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency 1015845500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate 0.016598 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_misses 87430 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_refs 59.267660 # Average number of references to valid blocks.
|
|
system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.demand_accesses 5267542 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_avg_miss_latency 14619.415532 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_hits 5180112 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_miss_latency 1278175500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_rate 0.016598 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_misses 87430 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_miss_latency 1015845500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_rate 0.016598 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_misses 87430 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.overall_accesses 5267542 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_avg_miss_latency 14619.415532 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency 11618.958024 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu1.icache.overall_hits 5180112 # number of overall hits
|
|
system.cpu1.icache.overall_miss_latency 1278175500 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_rate 0.016598 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_misses 87430 # number of overall misses
|
|
system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_miss_latency 1015845500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_rate 0.016598 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_misses 87430 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu1.icache.replacements 86890 # number of replacements
|
|
system.cpu1.icache.sampled_refs 87402 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu1.icache.tagsinuse 419.405623 # Cycle average of tags in use
|
|
system.cpu1.icache.total_refs 5180112 # Total number of references to valid blocks.
|
|
system.cpu1.icache.warmup_cycle 1967879772000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.writebacks 0 # number of writebacks
|
|
system.cpu1.idle_fraction 0.994655 # Percentage of idle cycles
|
|
system.cpu1.itb.accesses 1397499 # ITB accesses
|
|
system.cpu1.itb.acv 41 # ITB acv
|
|
system.cpu1.itb.hits 1396253 # ITB hits
|
|
system.cpu1.itb.misses 1246 # ITB misses
|
|
system.cpu1.kern.callpal 29501 # number of callpals executed
|
|
system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed
|
|
system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed
|
|
system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed
|
|
system.cpu1.kern.callpal_swpctx 365 1.24% 1.27% # number of callpals executed
|
|
system.cpu1.kern.callpal_tbi 10 0.03% 1.30% # number of callpals executed
|
|
system.cpu1.kern.callpal_wrent 7 0.02% 1.33% # number of callpals executed
|
|
system.cpu1.kern.callpal_swpipl 24142 81.83% 83.16% # number of callpals executed
|
|
system.cpu1.kern.callpal_rdps 2172 7.36% 90.52% # number of callpals executed
|
|
system.cpu1.kern.callpal_wrkgp 1 0.00% 90.53% # number of callpals executed
|
|
system.cpu1.kern.callpal_wrusp 3 0.01% 90.54% # number of callpals executed
|
|
system.cpu1.kern.callpal_rdusp 2 0.01% 90.54% # number of callpals executed
|
|
system.cpu1.kern.callpal_whami 3 0.01% 90.55% # number of callpals executed
|
|
system.cpu1.kern.callpal_rti 2594 8.79% 99.35% # number of callpals executed
|
|
system.cpu1.kern.callpal_callsys 161 0.55% 99.89% # number of callpals executed
|
|
system.cpu1.kern.callpal_imb 31 0.11% 100.00% # number of callpals executed
|
|
system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.hwrei 36051 # number of hwrei instructions executed
|
|
system.cpu1.kern.inst.quiesce 2351 # number of quiesce instructions executed
|
|
system.cpu1.kern.ipl_count 28808 # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count_0 9172 31.84% 31.84% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count_22 1980 6.87% 38.71% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count_30 91 0.32% 39.03% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count_31 17565 60.97% 100.00% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_good 20308 # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good_0 9164 45.13% 45.13% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good_22 1980 9.75% 54.87% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good_30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good_31 9073 44.68% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_ticks 1971683837000 # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks_0 1927969399500 97.78% 97.78% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks_22 511268500 0.03% 97.81% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks_30 58584000 0.00% 97.81% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks_31 43144585000 2.19% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_used_0 0.999128 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used_31 0.516539 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.mode_good_kernel 532
|
|
system.cpu1.kern.mode_good_user 516
|
|
system.cpu1.kern.mode_good_idle 16
|
|
system.cpu1.kern.mode_switch_kernel 880 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch_user 516 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch_idle 2081 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch_good 1.612234 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good_kernel 0.604545 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good_idle 0.007689 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_ticks_kernel 4597806000 0.23% 0.23% # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks_user 1703603000 0.09% 0.32% # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks_idle 1964669629000 99.68% 100.00% # number of ticks spent at the given mode
|
|
system.cpu1.kern.swap_context 366 # number of times the context was actually changed
|
|
system.cpu1.kern.syscall 102 # number of syscalls executed
|
|
system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed
|
|
system.cpu1.kern.syscall_3 11 10.78% 12.75% # number of syscalls executed
|
|
system.cpu1.kern.syscall_4 1 0.98% 13.73% # number of syscalls executed
|
|
system.cpu1.kern.syscall_6 12 11.76% 25.49% # number of syscalls executed
|
|
system.cpu1.kern.syscall_17 5 4.90% 30.39% # number of syscalls executed
|
|
system.cpu1.kern.syscall_19 4 3.92% 34.31% # number of syscalls executed
|
|
system.cpu1.kern.syscall_20 2 1.96% 36.27% # number of syscalls executed
|
|
system.cpu1.kern.syscall_23 2 1.96% 38.24% # number of syscalls executed
|
|
system.cpu1.kern.syscall_24 2 1.96% 40.20% # number of syscalls executed
|
|
system.cpu1.kern.syscall_33 3 2.94% 43.14% # number of syscalls executed
|
|
system.cpu1.kern.syscall_45 15 14.71% 57.84% # number of syscalls executed
|
|
system.cpu1.kern.syscall_47 2 1.96% 59.80% # number of syscalls executed
|
|
system.cpu1.kern.syscall_48 3 2.94% 62.75% # number of syscalls executed
|
|
system.cpu1.kern.syscall_54 1 0.98% 63.73% # number of syscalls executed
|
|
system.cpu1.kern.syscall_59 2 1.96% 65.69% # number of syscalls executed
|
|
system.cpu1.kern.syscall_71 22 21.57% 87.25% # number of syscalls executed
|
|
system.cpu1.kern.syscall_74 7 6.86% 94.12% # number of syscalls executed
|
|
system.cpu1.kern.syscall_90 1 0.98% 95.10% # number of syscalls executed
|
|
system.cpu1.kern.syscall_92 2 1.96% 97.06% # number of syscalls executed
|
|
system.cpu1.kern.syscall_132 2 1.96% 99.02% # number of syscalls executed
|
|
system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed
|
|
system.cpu1.not_idle_fraction 0.005345 # Percentage of non-idle cycles
|
|
system.cpu1.numCycles 3943367734 # number of cpu cycles simulated
|
|
system.cpu1.num_insts 5264352 # Number of instructions executed
|
|
system.cpu1.num_refs 1703685 # Number of memory references
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iocache.ReadReq_accesses 178 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_avg_miss_latency 115196.617978 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency 63196.617978 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_miss_latency 20504998 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_misses 178 # number of ReadReq misses
|
|
system.iocache.ReadReq_mshr_miss_latency 11248998 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_misses 178 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_avg_miss_latency 137906.834954 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency 85903.204082 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_miss_latency 5730304806 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_misses 41552 # number of WriteReq misses
|
|
system.iocache.WriteReq_mshr_miss_latency 3569449936 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
|
|
system.iocache.avg_blocked_cycles_no_mshrs 6168.564107 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.blocked_no_mshrs 10459 # number of cycles access was blocked
|
|
system.iocache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles_no_mshrs 64517012 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.demand_accesses 41730 # number of demand (read+write) accesses
|
|
system.iocache.demand_avg_miss_latency 137809.964150 # average overall miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency
|
|
system.iocache.demand_hits 0 # number of demand (read+write) hits
|
|
system.iocache.demand_miss_latency 5750809804 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_rate 1 # miss rate for demand accesses
|
|
system.iocache.demand_misses 41730 # number of demand (read+write) misses
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.iocache.demand_mshr_miss_latency 3580698934 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_misses 41730 # number of demand (read+write) MSHR misses
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.overall_accesses 41730 # number of overall (read+write) accesses
|
|
system.iocache.overall_avg_miss_latency 137809.964150 # average overall miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency 85806.348766 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.iocache.overall_hits 0 # number of overall hits
|
|
system.iocache.overall_miss_latency 5750809804 # number of overall miss cycles
|
|
system.iocache.overall_miss_rate 1 # miss rate for overall accesses
|
|
system.iocache.overall_misses 41730 # number of overall misses
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.iocache.overall_mshr_miss_latency 3580698934 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.iocache.replacements 41698 # number of replacements
|
|
system.iocache.sampled_refs 41714 # Sample count of references to valid blocks.
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.iocache.tagsinuse 0.582076 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.warmup_cycle 1762323729000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.writebacks 41520 # number of writebacks
|
|
system.l2c.ReadExReq_accesses 306796 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_avg_miss_latency 52002.653229 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40002.653229 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_miss_latency 15954206000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_misses 306796 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_mshr_miss_latency 12272654000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_misses 306796 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadReq_accesses 2090247 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_avg_miss_latency 52016.274350 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 40016.322096 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_hits 1782800 # number of ReadReq hits
|
|
system.l2c.ReadReq_miss_latency 15992247500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_rate 0.147086 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_misses 307447 # number of ReadReq misses
|
|
system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_miss_latency 12302458000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_rate 0.147081 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_misses 307436 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable_latency 789200000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.UpgradeReq_accesses 127300 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_avg_miss_latency 50741.146897 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 40004.988217 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_miss_latency 6459348000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_misses 127300 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency 5092635000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_misses 127300 # number of UpgradeReq MSHR misses
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_mshr_uncacheable_latency 1381237000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.Writeback_accesses 430395 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_hits 430395 # number of Writeback hits
|
|
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.l2c.avg_refs 4.558799 # Average number of references to valid blocks.
|
|
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.demand_accesses 2397043 # number of demand (read+write) accesses
|
|
system.l2c.demand_avg_miss_latency 52009.471007 # average overall miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency
|
|
system.l2c.demand_hits 1782800 # number of demand (read+write) hits
|
|
system.l2c.demand_miss_latency 31946453500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_rate 0.256250 # miss rate for demand accesses
|
|
system.l2c.demand_misses 614243 # number of demand (read+write) misses
|
|
system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_miss_latency 24575112000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_rate 0.256246 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_misses 614232 # number of demand (read+write) MSHR misses
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.overall_accesses 2397043 # number of overall (read+write) accesses
|
|
system.l2c.overall_avg_miss_latency 52009.471007 # average overall miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency 40009.494784 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_hits 1782800 # number of overall hits
|
|
system.l2c.overall_miss_latency 31946453500 # number of overall miss cycles
|
|
system.l2c.overall_miss_rate 0.256250 # miss rate for overall accesses
|
|
system.l2c.overall_misses 614243 # number of overall misses
|
|
system.l2c.overall_mshr_hits 11 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_miss_latency 24575112000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_rate 0.256246 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_misses 614232 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_uncacheable_latency 2170437000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.l2c.replacements 399043 # number of replacements
|
|
system.l2c.sampled_refs 430765 # Sample count of references to valid blocks.
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.l2c.tagsinuse 30865.823052 # Cycle average of tags in use
|
|
system.l2c.total_refs 1963771 # Total number of references to valid blocks.
|
|
system.l2c.warmup_cycle 10912833000 # Cycle when the warmup percentage was hit.
|
|
system.l2c.writebacks 123178 # number of writebacks
|
|
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
|
|
---------- End Simulation Statistics ----------
|