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gem5/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
Steve Reinhardt 9e45ada171 stats: update stats for preceding coherence changes 
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
2010-09-09 14:40:19 -04:00

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---------- Begin Simulation Statistics ----------
host_inst_rate 105247 # Simulator instruction rate (inst/s)
host_mem_usage 214344 # Number of bytes of host memory used
host_seconds 17321.56 # Real time elapsed on the host
host_tick_rate 40567294 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1823043370 # Number of instructions simulated
sim_seconds 0.702689 # Number of seconds simulated
sim_ticks 702688811500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 239396241 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 292393914 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 3599 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 28358143 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 232710596 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 347019771 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 49329086 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 266706457 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 67430429 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 1305107182 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.539328 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.193562 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 596079504 45.67% 45.67% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 274005611 20.99% 66.67% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 176024939 13.49% 80.16% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 67867193 5.20% 85.36% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 46132467 3.53% 88.89% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 33942844 2.60% 91.49% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 19726349 1.51% 93.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 23897846 1.83% 94.83% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 67430429 5.17% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1305107182 # Number of insts commited each cycle
system.cpu.commit.COM:count 2008987604 # Number of instructions committed
system.cpu.commit.COM:loads 511595302 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 722390433 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 28346322 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 694586134 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
system.cpu.cpi 0.770896 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.770896 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 8 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 8 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 463358852 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 37466.685698 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34710.185206 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 461425148 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 72449480000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.004173 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1933704 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 474303 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 50656079000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003150 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1459401 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 38589.512736 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36524.349360 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 210236618 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 21543675991 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.002648 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 558278 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 484005 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2712773000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000352 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 74273 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6041.666667 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 14500 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 438.700297 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 72500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 14500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 674153748 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 37718.232311 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34798.041826 # average overall mshr miss latency
system.cpu.dcache.demand_hits 671661766 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 93993155991 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.003696 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2491982 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 958308 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 53368852000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002275 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1533674 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999781 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4095.104320 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 674153748 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 37718.232311 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34798.041826 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 671661766 # number of overall hits
system.cpu.dcache.overall_miss_latency 93993155991 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.003696 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2491982 # number of overall misses
system.cpu.dcache.overall_mshr_hits 958308 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 53368852000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002275 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1533674 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 1526954 # number of replacements
system.cpu.dcache.sampled_refs 1531050 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.104320 # Cycle average of tags in use
system.cpu.dcache.total_refs 671672090 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 274011000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 74616 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 31207203 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 12052 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 30419221 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 2934529925 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 711825403 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 561989361 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 100109049 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 45710 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 85215 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 772921338 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 772287215 # DTB hits
system.cpu.dtb.data_misses 634123 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 514592222 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 513995856 # DTB read hits
system.cpu.dtb.read_misses 596366 # DTB read misses
system.cpu.dtb.write_accesses 258329116 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 258291359 # DTB write hits
system.cpu.dtb.write_misses 37757 # DTB write misses
system.cpu.fetch.Branches 347019771 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 347236210 # Number of cache lines fetched
system.cpu.fetch.Cycles 925540339 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 4572630 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 3016868050 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 28795074 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.246923 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 347236210 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 288725327 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.146660 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1405216231 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.146907 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.027321 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 826912311 58.85% 58.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 54085812 3.85% 62.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 40125133 2.86% 65.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 63577185 4.52% 70.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 121409089 8.64% 78.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 34600240 2.46% 81.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 37932193 2.70% 83.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7024441 0.50% 84.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 219549827 15.62% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1405216231 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 347236210 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 15852.092893 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11646.295350 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 347225531 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 169284500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 10679 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 894 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 113959000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 9785 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 35489.118050 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 347236210 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 15852.092893 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11646.295350 # average overall mshr miss latency
system.cpu.icache.demand_hits 347225531 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 169284500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses
system.cpu.icache.demand_misses 10679 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 894 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 113959000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 9785 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.787162 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1612.107078 # Average occupied blocks per context
system.cpu.icache.overall_accesses 347236210 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 15852.092893 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11646.295350 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 347225531 # number of overall hits
system.cpu.icache.overall_miss_latency 169284500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses
system.cpu.icache.overall_misses 10679 # number of overall misses
system.cpu.icache.overall_mshr_hits 894 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 113959000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 9785 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 8113 # number of replacements
system.cpu.icache.sampled_refs 9784 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1612.107078 # Cycle average of tags in use
system.cpu.icache.total_refs 347225531 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 161393 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 274718833 # Number of branches executed
system.cpu.iew.EXEC:nop 329034713 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.424505 # Inst execution rate
system.cpu.iew.EXEC:refs 773457001 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 258330075 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1632862772 # num instructions consuming a value
system.cpu.iew.WB:count 2000954749 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.695811 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1136164328 # num instructions producing a value
system.cpu.iew.WB:rate 1.423784 # insts written-back per cycle
system.cpu.iew.WB:sent 2001905607 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 30878599 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 3451748 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 655963109 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 64 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 51733 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 302851236 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2713712461 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 515126926 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 84126603 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 2001967300 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 131046 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 1380 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 100109049 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 140868 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 50632865 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 227 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 3782 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 4125 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 144367807 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 92056105 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 3782 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 787958 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 30090641 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.297191 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.297191 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1203926458 57.71% 57.71% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 17656 0.00% 57.71% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.71% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27851408 1.34% 59.05% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254704 0.40% 59.44% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204646 0.35% 59.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 555703221 26.64% 86.43% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 283133054 13.57% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 2086093903 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 35524455 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.017029 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 5029 0.01% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 26764066 75.34% 75.35% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 8755360 24.65% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 1405216231 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.484536 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.637275 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 532926303 37.92% 37.92% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 283749414 20.19% 58.12% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 275573113 19.61% 77.73% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 156459284 11.13% 88.86% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 63140415 4.49% 93.36% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 47210297 3.36% 96.72% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 32913048 2.34% 99.06% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 10225878 0.73% 99.79% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 3018479 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1405216231 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.484365 # Inst issue rate
system.cpu.iq.iqInstsAdded 2384677684 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 2086093903 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 561606840 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 12399741 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 517624785 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 347236419 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 347236210 # ITB hits
system.cpu.itb.fetch_misses 209 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 71649 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 35091.445798 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.513824 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 2514267000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 71649 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297462000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 71649 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 1469186 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34207.393582 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.426347 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 29045 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 49263470000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.980231 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1440141 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 44644985000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980231 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1440141 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 2624 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34296.875000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31001.905488 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 89995000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 2624 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 81349000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 2624 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 74616 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 74616 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7200 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.023753 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 36000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 1540835 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34249.291899 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.904557 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 29045 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 51777737000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.981150 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 1511790 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 46942447000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.981150 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 1511790 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.927958 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.046323 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 30407.323461 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 1517.897239 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 1540835 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34249.291899 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.904557 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 29045 # number of overall hits
system.cpu.l2cache.overall_miss_latency 51777737000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.981150 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 1511790 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 46942447000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.981150 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 1511790 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 1474292 # number of replacements
system.cpu.l2cache.sampled_refs 1506959 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 31925.220700 # Cycle average of tags in use
system.cpu.l2cache.total_refs 35795 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 66899 # number of writebacks
system.cpu.memDep0.conflictingLoads 126385471 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 12290638 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 655963109 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 302851236 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 1405377624 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 20016233 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 673555 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 725805122 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 10749358 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 18 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 3307765426 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2838518766 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 1890285688 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 546657671 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 100109049 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 12606278 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 505316618 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 21878 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 2883 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 26993135 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 69 # count of temporary serializing insts renamed
system.cpu.timesIdled 4180 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
---------- End Simulation Statistics ----------
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