98c94cfe3c
The necessary companion conversion of Ruby objects generated by SLICC are converted to M5 SimObjects in the following patch, so this patch alone does not compile. Conversion of Garnet network models is also handled in a separate patch; that code is temporarily disabled from compiling to allow testing of interim code.
144 lines
5.1 KiB
Python
144 lines
5.1 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ron Dreslinski
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# Brad Beckmann
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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import os, optparse, sys
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addToPath('../common')
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parser = optparse.OptionParser()
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parser.add_option("-a", "--atomic", action="store_true",
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help="Use atomic (non-timing) mode")
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parser.add_option("-b", "--blocking", action="store_true",
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help="Use blocking caches")
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parser.add_option("-l", "--maxloads", metavar="N", default=0,
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help="Stop after N loads")
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parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
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metavar="T",
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help="Stop after T ticks")
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parser.add_option("-t", "--testers", type="int", metavar="N", default=1,
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help="number of testers/cores")
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parser.add_option("-f", "--functional", type="int", default=0,
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metavar="PCT",
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help="Target percentage of functional accesses "
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"[default: %default]")
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parser.add_option("-u", "--uncacheable", type="int", default=0,
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metavar="PCT",
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help="Target percentage of uncacheable accesses "
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"[default: %default]")
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parser.add_option("--progress", type="int", default=1000,
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metavar="NLOADS",
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help="Progress message interval "
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"[default: %default]")
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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block_size = 64
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if options.testers > block_size:
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print "Error: Number of testers %d limited to %d because of false sharing" \
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% (options.testers, block_size)
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sys.exit(1)
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cpus = [ MemTest(atomic=options.atomic, max_loads=options.maxloads, \
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percent_functional=options.functional, \
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percent_uncacheable=options.uncacheable, \
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progress_interval=options.progress) \
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for i in xrange(options.testers) ]
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system = System(cpu = cpus,
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funcmem = PhysicalMemory(),
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physmem = PhysicalMemory())
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class L1Cache(RubyCache):
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assoc = 2
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latency = 3
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size = 32768
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class L2Cache(RubyCache):
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assoc = 16
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latency = 15
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size = 1048576
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class CrossbarTopology(Topology):
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connections="hi"
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for cpu in cpus:
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l1_cntrl = L1Cache_Controller()
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cpu_seq = RubySequencer(controller=l1_cntrl,
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icache=L1Cache(controller=l1_cntrl),
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dcache=L1Cache(controller=l1_cntrl))
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cpu.controller = l1_cntrl
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cpu.sequencer = cpu_seq
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cpu.test = cpu_seq.port
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cpu_seq.funcmem_port = system.physmem.port
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cpu.functional = system.funcmem.port
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dir_cntrl = Directory_Controller(directory=RubyDirectoryMemory(),
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memory_control=RubyMemoryControl())
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network = SimpleNetwork(topology=CrossbarTopology())
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system.ruby = RubySystem(network = network,
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profiler = RubyProfiler(),
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tracer = RubyTracer(),
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debug = RubyDebug())
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# -----------------------
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# run simulation
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# -----------------------
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root = Root( system = system )
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if options.atomic:
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root.system.mem_mode = 'atomic'
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else:
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency('1ns')
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# instantiate configuration
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m5.instantiate(root)
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# simulate until program terminates
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exit_event = m5.simulate(options.maxtick)
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print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
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