18142df5b9
In SLICC, in order to define a type a data type for which it should not generate any code, the keyword external_type is used. For those data types for which code should be generated, the keyword structure is used. This patch eliminates the use of keyword external_type for defining structures. structure key word can now have an optional attribute external, which would be used for figuring out whether or not to generate the code for this structure. Also, now structures can have functions as well data members in them.
564 lines
18 KiB
Text
564 lines
18 KiB
Text
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/*
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* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* $Id: MOESI_CMP_token-dir.sm 1.6 05/01/19 15:48:35-06:00 mikem@royal16.cs.wisc.edu $
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*/
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// This file is copied from Yasuko Watanabe's prefetch / memory protocol
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// Copied here by aep 12/14/07
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machine(Directory, "MESI_CMP_filter_directory protocol")
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: DirectoryMemory * directory,
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MemoryControl * memBuffer,
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int to_mem_ctrl_latency = 1,
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int directory_latency = 6
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{
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MessageBuffer requestToDir, network="From", virtual_network="0", ordered="false";
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MessageBuffer responseToDir, network="From", virtual_network="1", ordered="false";
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MessageBuffer requestFromDir, network="To", virtual_network="0", ordered="false";
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MessageBuffer responseFromDir, network="To", virtual_network="1", ordered="false";
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// STATES
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state_declaration(State, desc="Directory states", default="Directory_State_I") {
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// Base states
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I, AccessPermission:Read_Write, desc="dir is the owner and memory is up-to-date, all other copies are Invalid";
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ID, AccessPermission:Busy, desc="Intermediate state for DMA_READ when in I";
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ID_W, AccessPermission:Busy, desc="Intermediate state for DMA_WRITE when in I";
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M, AccessPermission:Invalid, desc="memory copy may be stale, i.e. other modified copies may exist";
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IM, AccessPermission:Busy, desc="Intermediate State I>M";
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MI, AccessPermission:Busy, desc="Intermediate State M>I";
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M_DRD, AccessPermission:Busy, desc="Intermediate State when there is a dma read";
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M_DRDI, AccessPermission:Busy, desc="Intermediate State when there is a dma read";
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M_DWR, AccessPermission:Busy, desc="Intermediate State when there is a dma write";
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M_DWRI, AccessPermission:Busy, desc="Intermediate State when there is a dma write";
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}
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// Events
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enumeration(Event, desc="Directory events") {
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Fetch, desc="A memory fetch arrives";
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Data, desc="writeback data arrives";
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Memory_Data, desc="Fetched data from memory arrives";
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Memory_Ack, desc="Writeback Ack from memory arrives";
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//added by SS for dma
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DMA_READ, desc="A DMA Read memory request";
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DMA_WRITE, desc="A DMA Write memory request";
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CleanReplacement, desc="Clean Replacement in L2 cache";
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}
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// TYPES
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// DirectoryEntry
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structure(Entry, desc="...", interface="AbstractEntry") {
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State DirectoryState, desc="Directory state";
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DataBlock DataBlk, desc="data for the block";
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NetDest Sharers, desc="Sharers for this block";
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NetDest Owner, desc="Owner of this block";
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}
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// TBE entries for DMA requests
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structure(TBE, desc="TBE entries for outstanding DMA requests") {
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Address PhysicalAddress, desc="physical address";
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State TBEState, desc="Transient State";
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DataBlock DataBlk, desc="Data to be written (DMA write only)";
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int Len, desc="...";
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}
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structure(TBETable, external="yes") {
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TBE lookup(Address);
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void allocate(Address);
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void deallocate(Address);
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bool isPresent(Address);
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}
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// ** OBJECTS **
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TBETable TBEs, template_hack="<Directory_TBE>";
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void set_tbe(TBE tbe);
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void unset_tbe();
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Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
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return static_cast(Entry, directory[addr]);
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}
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State getState(TBE tbe, Address addr) {
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if (is_valid(tbe)) {
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return tbe.TBEState;
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} else if (directory.isPresent(addr)) {
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return getDirectoryEntry(addr).DirectoryState;
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} else {
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return State:I;
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}
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}
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void setState(TBE tbe, Address addr, State state) {
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if (is_valid(tbe)) {
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tbe.TBEState := state;
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}
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if (directory.isPresent(addr)) {
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if (state == State:I) {
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assert(getDirectoryEntry(addr).Owner.count() == 0);
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assert(getDirectoryEntry(addr).Sharers.count() == 0);
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} else if (state == State:M) {
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assert(getDirectoryEntry(addr).Owner.count() == 1);
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assert(getDirectoryEntry(addr).Sharers.count() == 0);
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}
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getDirectoryEntry(addr).DirectoryState := state;
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}
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}
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bool isGETRequest(CoherenceRequestType type) {
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return (type == CoherenceRequestType:GETS) ||
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(type == CoherenceRequestType:GET_INSTR) ||
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(type == CoherenceRequestType:GETX);
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}
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// ** OUT_PORTS **
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out_port(responseNetwork_out, ResponseMsg, responseFromDir);
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out_port(memQueue_out, MemoryMsg, memBuffer);
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// ** IN_PORTS **
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in_port(requestNetwork_in, RequestMsg, requestToDir) {
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if (requestNetwork_in.isReady()) {
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peek(requestNetwork_in, RequestMsg) {
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assert(in_msg.Destination.isElement(machineID));
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if (isGETRequest(in_msg.Type)) {
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trigger(Event:Fetch, in_msg.Address, TBEs[in_msg.Address]);
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} else if (in_msg.Type == CoherenceRequestType:DMA_READ) {
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trigger(Event:DMA_READ, makeLineAddress(in_msg.Address),
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TBEs[makeLineAddress(in_msg.Address)]);
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} else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) {
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trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Address),
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TBEs[makeLineAddress(in_msg.Address)]);
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} else {
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DPRINTF(RubySlicc, "%s\n", in_msg);
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error("Invalid message");
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}
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}
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}
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}
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in_port(responseNetwork_in, ResponseMsg, responseToDir) {
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if (responseNetwork_in.isReady()) {
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peek(responseNetwork_in, ResponseMsg) {
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assert(in_msg.Destination.isElement(machineID));
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if (in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
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trigger(Event:Data, in_msg.Address, TBEs[in_msg.Address]);
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} else if (in_msg.Type == CoherenceResponseType:ACK) {
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trigger(Event:CleanReplacement, in_msg.Address, TBEs[in_msg.Address]);
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} else {
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DPRINTF(RubySlicc, "%s\n", in_msg.Type);
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error("Invalid message");
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}
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}
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}
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}
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// off-chip memory request/response is done
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in_port(memQueue_in, MemoryMsg, memBuffer) {
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if (memQueue_in.isReady()) {
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peek(memQueue_in, MemoryMsg) {
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if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
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trigger(Event:Memory_Data, in_msg.Address, TBEs[in_msg.Address]);
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} else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
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trigger(Event:Memory_Ack, in_msg.Address, TBEs[in_msg.Address]);
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} else {
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DPRINTF(RubySlicc, "%s\n", in_msg.Type);
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error("Invalid message");
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}
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}
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}
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}
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// Actions
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action(a_sendAck, "a", desc="Send ack to L2") {
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peek(responseNetwork_in, ResponseMsg) {
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enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
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out_msg.Address := address;
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out_msg.Type := CoherenceResponseType:MEMORY_ACK;
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out_msg.Sender := machineID;
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out_msg.Destination.add(in_msg.Sender);
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out_msg.MessageSize := MessageSizeType:Response_Control;
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}
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}
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}
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action(d_sendData, "d", desc="Send data to requestor") {
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peek(memQueue_in, MemoryMsg) {
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enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
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out_msg.Address := address;
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out_msg.Type := CoherenceResponseType:MEMORY_DATA;
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out_msg.Sender := machineID;
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out_msg.Destination.add(in_msg.OriginalRequestorMachId);
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.Dirty := false;
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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}
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// Actions
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action(aa_sendAck, "aa", desc="Send ack to L2") {
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peek(memQueue_in, MemoryMsg) {
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enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
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out_msg.Address := address;
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out_msg.Type := CoherenceResponseType:MEMORY_ACK;
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out_msg.Sender := machineID;
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out_msg.Destination.add(in_msg.OriginalRequestorMachId);
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out_msg.MessageSize := MessageSizeType:Response_Control;
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}
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}
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}
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action(j_popIncomingRequestQueue, "j", desc="Pop incoming request queue") {
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requestNetwork_in.dequeue();
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}
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action(k_popIncomingResponseQueue, "k", desc="Pop incoming request queue") {
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responseNetwork_in.dequeue();
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}
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action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
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memQueue_in.dequeue();
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}
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action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
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peek(requestNetwork_in, RequestMsg) {
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enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
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out_msg.Address := address;
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out_msg.Type := MemoryRequestType:MEMORY_READ;
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out_msg.Sender := machineID;
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out_msg.OriginalRequestorMachId := in_msg.Requestor;
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out_msg.MessageSize := in_msg.MessageSize;
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out_msg.Prefetch := in_msg.Prefetch;
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out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
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DPRINTF(RubySlicc, "%s\n", out_msg);
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}
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}
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}
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action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") {
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peek(responseNetwork_in, ResponseMsg) {
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enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
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out_msg.Address := address;
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out_msg.Type := MemoryRequestType:MEMORY_WB;
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out_msg.Sender := machineID;
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out_msg.OriginalRequestorMachId := in_msg.Sender;
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.MessageSize := in_msg.MessageSize;
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//out_msg.Prefetch := in_msg.Prefetch;
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DPRINTF(RubySlicc, "%s\n", out_msg);
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}
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}
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}
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action(m_writeDataToMemory, "m", desc="Write dirty writeback to memory") {
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peek(responseNetwork_in, ResponseMsg) {
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getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
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DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
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in_msg.Address, in_msg.DataBlk);
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}
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}
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//added by SS for dma
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action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") {
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peek(requestNetwork_in, RequestMsg) {
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enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
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out_msg.Address := address;
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out_msg.Type := MemoryRequestType:MEMORY_READ;
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out_msg.Sender := machineID;
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out_msg.OriginalRequestorMachId := machineID;
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out_msg.MessageSize := in_msg.MessageSize;
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out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
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DPRINTF(RubySlicc, "%s\n", out_msg);
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}
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}
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}
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action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") {
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requestNetwork_in.dequeue();
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}
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action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
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peek(memQueue_in, MemoryMsg) {
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enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
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out_msg.Address := address;
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out_msg.Type := CoherenceResponseType:DATA;
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out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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out_msg.Destination.add(map_Address_to_DMA(address));
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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}
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action(dw_writeDMAData, "dw", desc="DMA Write data to memory") {
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peek(requestNetwork_in, RequestMsg) {
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getDirectoryEntry(address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
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}
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}
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action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") {
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peek(requestNetwork_in, RequestMsg) {
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enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
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out_msg.Address := address;
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out_msg.Type := MemoryRequestType:MEMORY_WB;
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out_msg.OriginalRequestorMachId := machineID;
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//out_msg.DataBlk := in_msg.DataBlk;
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out_msg.DataBlk.copyPartial(in_msg.DataBlk, addressOffset(address), in_msg.Len);
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out_msg.MessageSize := in_msg.MessageSize;
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//out_msg.Prefetch := in_msg.Prefetch;
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DPRINTF(RubySlicc, "%s\n", out_msg);
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}
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}
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}
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action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") {
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enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
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out_msg.Address := address;
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out_msg.Type := CoherenceResponseType:ACK;
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out_msg.Destination.add(map_Address_to_DMA(address));
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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action(z_recycleRequestQueue, "z", desc="recycle request queue") {
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requestNetwork_in.recycle();
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}
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action(zz_recycleDMAQueue, "zz", desc="recycle DMA queue") {
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requestNetwork_in.recycle();
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}
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action(e_ownerIsRequestor, "e", desc="The owner is now the requestor") {
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peek(requestNetwork_in, RequestMsg) {
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getDirectoryEntry(address).Owner.clear();
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getDirectoryEntry(address).Owner.add(in_msg.Requestor);
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}
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}
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action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
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peek(requestNetwork_in, RequestMsg) {
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enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) {
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out_msg.Address := address;
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out_msg.Type := CoherenceResponseType:INV;
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out_msg.Sender := machineID;
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out_msg.Destination := getDirectoryEntry(address).Owner;
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out_msg.MessageSize := MessageSizeType:Response_Control;
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}
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}
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}
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action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") {
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peek(responseNetwork_in, ResponseMsg) {
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enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
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out_msg.Address := address;
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out_msg.Type := CoherenceResponseType:DATA;
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out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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out_msg.Destination.add(map_Address_to_DMA(address));
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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}
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action(c_clearOwner, "c", desc="Clear the owner field") {
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getDirectoryEntry(address).Owner.clear();
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}
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action(v_allocateTBE, "v", desc="Allocate TBE") {
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peek(requestNetwork_in, RequestMsg) {
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TBEs.allocate(address);
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set_tbe(TBEs[address]);
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tbe.DataBlk := in_msg.DataBlk;
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tbe.PhysicalAddress := in_msg.Address;
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tbe.Len := in_msg.Len;
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}
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}
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action(dwt_writeDMADataFromTBE, "dwt", desc="DMA Write data to memory from TBE") {
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assert(is_valid(tbe));
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//getDirectoryEntry(address).DataBlk.copyPartial(tbe.DataBlk, tbe.Offset, tbe.Len);
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getDirectoryEntry(address).DataBlk.copyPartial(tbe.DataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
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}
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action(qw_queueMemoryWBRequest_partialTBE, "qwt", desc="Queue off-chip writeback request") {
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peek(responseNetwork_in, ResponseMsg) {
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enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
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assert(is_valid(tbe));
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out_msg.Address := address;
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out_msg.Type := MemoryRequestType:MEMORY_WB;
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out_msg.OriginalRequestorMachId := in_msg.Sender;
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//out_msg.DataBlk := in_msg.DataBlk;
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//out_msg.DataBlk.copyPartial(tbe.DataBlk, tbe.Offset, tbe.Len);
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out_msg.DataBlk.copyPartial(tbe.DataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
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out_msg.MessageSize := in_msg.MessageSize;
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//out_msg.Prefetch := in_msg.Prefetch;
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DPRINTF(RubySlicc, "%s\n", out_msg);
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}
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}
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}
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action(w_deallocateTBE, "w", desc="Deallocate TBE") {
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TBEs.deallocate(address);
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unset_tbe();
|
|
}
|
|
|
|
|
|
// TRANSITIONS
|
|
|
|
|
|
transition(I, Fetch, IM) {
|
|
qf_queueMemoryFetchRequest;
|
|
e_ownerIsRequestor;
|
|
j_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(IM, Memory_Data, M) {
|
|
d_sendData;
|
|
l_popMemQueue;
|
|
}
|
|
//added by SS
|
|
transition(M, CleanReplacement, I) {
|
|
c_clearOwner;
|
|
a_sendAck;
|
|
k_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(M, Data, MI) {
|
|
m_writeDataToMemory;
|
|
qw_queueMemoryWBRequest;
|
|
k_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(MI, Memory_Ack, I) {
|
|
c_clearOwner;
|
|
aa_sendAck;
|
|
l_popMemQueue;
|
|
}
|
|
|
|
|
|
//added by SS for dma support
|
|
transition(I, DMA_READ, ID) {
|
|
qf_queueMemoryFetchRequestDMA;
|
|
j_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(ID, Memory_Data, I) {
|
|
dr_sendDMAData;
|
|
l_popMemQueue;
|
|
}
|
|
|
|
transition(I, DMA_WRITE, ID_W) {
|
|
dw_writeDMAData;
|
|
qw_queueMemoryWBRequest_partial;
|
|
j_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(ID_W, Memory_Ack, I) {
|
|
da_sendDMAAck;
|
|
l_popMemQueue;
|
|
}
|
|
|
|
transition({ID, ID_W, M_DRDI, M_DWRI, IM, MI}, {Fetch, Data} ) {
|
|
z_recycleRequestQueue;
|
|
}
|
|
|
|
transition({ID, ID_W, M_DRD, M_DRDI, M_DWR, M_DWRI, IM, MI}, {DMA_WRITE, DMA_READ} ) {
|
|
zz_recycleDMAQueue;
|
|
}
|
|
|
|
|
|
transition(M, DMA_READ, M_DRD) {
|
|
inv_sendCacheInvalidate;
|
|
j_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(M_DRD, Data, M_DRDI) {
|
|
drp_sendDMAData;
|
|
m_writeDataToMemory;
|
|
qw_queueMemoryWBRequest;
|
|
k_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(M_DRDI, Memory_Ack, I) {
|
|
aa_sendAck;
|
|
c_clearOwner;
|
|
l_popMemQueue;
|
|
}
|
|
|
|
transition(M, DMA_WRITE, M_DWR) {
|
|
v_allocateTBE;
|
|
inv_sendCacheInvalidate;
|
|
j_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(M_DWR, Data, M_DWRI) {
|
|
m_writeDataToMemory;
|
|
qw_queueMemoryWBRequest_partialTBE;
|
|
k_popIncomingResponseQueue;
|
|
}
|
|
|
|
transition(M_DWRI, Memory_Ack, I) {
|
|
dwt_writeDMADataFromTBE;
|
|
aa_sendAck;
|
|
c_clearOwner;
|
|
da_sendDMAAck;
|
|
w_deallocateTBE;
|
|
l_popMemQueue;
|
|
}
|
|
|
|
}
|