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gem5/src/arch/arm
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Andreas Sandberg 17b47d35e1 arch: Move the ISA object to a separate section 
After making the ISA an independent SimObject, it is serialized
automatically by the Python world. Previously, this just resulted in
an empty ISA section. This patch moves the contents of the ISA to that
section and removes the explicit ISA serialization from the thread
contexts, which makes it behave like a normal SimObject during
serialization.

Note: This patch breaks checkpoint backwards compatibility! Use the
cpt_upgrader.py utility to upgrade old checkpoints to the new format.
2013-01-07 13:05:42 -05:00
..
insts arm: set movret_uop as conditional or unconditional control 2012-12-12 09:50:16 -06:00
isa arm: set uopSet_uop as conditional or unconditional control 2012-12-12 09:50:33 -06:00
linux base: Encapsulate the underlying fields in AddrRange 2013-01-07 13:05:38 -05:00
ArmInterrupts.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
ArmISA.py arm: Make ID registers ISA parameters 2013-01-07 13:05:35 -05:00
ArmNativeTrace.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
ArmSystem.py arm: Make ID registers ISA parameters 2013-01-07 13:05:35 -05:00
ArmTLB.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
decoder.cc Decoder: Remove the thread context get/set from the decoder. 2013-01-04 19:00:45 -06:00
decoder.hh Decoder: Remove the thread context get/set from the decoder. 2013-01-04 19:00:45 -06:00
faults.cc Implement Ali's review feedback. 2012-01-29 02:04:34 -08:00
faults.hh SE/FS: Get rid of FULL_SYSTEM in the ARM ISA. 2011-11-02 01:25:15 -07:00
interrupts.cc ARM: Implement ARM CPU interrupts 2010-06-02 12:58:16 -05:00
interrupts.hh Fix bugs due to interaction between SEV instructions and O3 pipeline 2011-08-19 15:08:07 -05:00
intregs.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
isa.cc arm: Make ID registers ISA parameters 2013-01-07 13:05:35 -05:00
isa.hh arch: Move the ISA object to a separate section 2013-01-07 13:05:42 -05:00
isa_traits.hh ISA: generic Linux thread info support 2012-11-02 11:32:00 -05:00
kernel_stats.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
locked_mem.hh o3: Fix issue with LLSC ordering and speculation 2013-01-07 13:05:33 -05:00
microcode_rom.hh arm: include missing file for arm 2009-04-21 15:40:26 -07:00
miscregs.cc gem5: Fix a number of incorrect case statements 2012-05-10 18:04:26 -05:00
miscregs.hh arm: Use a static_assert to test that miscRegName[] is complete 2012-09-25 11:49:40 -05:00
mmapped_ipr.hh Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
nativetrace.cc gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
nativetrace.hh ARM: Add vfpv3 support to native trace. 2011-05-04 20:38:26 -05:00
pagetable.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
process.cc MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
process.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
registers.hh O3: Clean up the O3 structures and try to pack them a bit better. 2012-06-05 01:23:09 -04:00
remote_gdb.cc ARM: Keep a copy of the fpscr len and stride fields in the decoder. 2013-01-04 18:09:35 -06:00
remote_gdb.hh MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
SConscript arch: Make the ISA class inherit from SimObject 2013-01-07 13:05:35 -05:00
SConsopts arm: add ARM support to M5 2009-04-05 18:53:15 -07:00
stacktrace.cc ARM: implement the ProcessInfo methods 2012-06-11 11:07:41 -04:00
stacktrace.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
system.cc arm: Make ID registers ISA parameters 2013-01-07 13:05:35 -05:00
system.hh ARM: Fix MPIDR and MIDR register implementation. 2012-06-05 01:23:10 -04:00
table_walker.cc sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
table_walker.hh sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
tlb.cc Port: Add protocol-agnostic ports in the port hierarchy 2012-10-15 08:12:35 -04:00
tlb.hh Port: Add protocol-agnostic ports in the port hierarchy 2012-10-15 08:12:35 -04:00
types.hh ARM: Fix issue with predicted next pc being wrong because of advance() ordering. 2012-06-29 11:18:28 -04:00
utility.cc cpu: Don't init simple and inorder CPUs if they are defered. 2012-06-05 14:20:13 -04:00
utility.hh Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
vtophys.cc MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
vtophys.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00