2e28da5583
Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
66 lines
2.5 KiB
Python
66 lines
2.5 KiB
Python
# -*- mode:python -*-
|
|
|
|
# Copyright (c) 2007-2008 The Florida State University
|
|
# All rights reserved.
|
|
#
|
|
# Redistribution and use in source and binary forms, with or without
|
|
# modification, are permitted provided that the following conditions are
|
|
# met: redistributions of source code must retain the above copyright
|
|
# notice, this list of conditions and the following disclaimer;
|
|
# redistributions in binary form must reproduce the above copyright
|
|
# notice, this list of conditions and the following disclaimer in the
|
|
# documentation and/or other materials provided with the distribution;
|
|
# neither the name of the copyright holders nor the names of its
|
|
# contributors may be used to endorse or promote products derived from
|
|
# this software without specific prior written permission.
|
|
#
|
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
#
|
|
# Authors: Stephen Hines
|
|
|
|
Import('*')
|
|
|
|
if env['TARGET_ISA'] == 'arm':
|
|
# Workaround for bug in SCons version > 0.97d20071212
|
|
# Scons bug id: 2006 M5 Bug id: 308
|
|
Dir('isa/formats')
|
|
Source('faults.cc')
|
|
Source('insts/branch.cc')
|
|
Source('insts/mem.cc')
|
|
Source('insts/pred_inst.cc')
|
|
Source('insts/static_inst.cc')
|
|
Source('nativetrace.cc')
|
|
Source('pagetable.cc')
|
|
Source('tlb.cc')
|
|
Source('vtophys.cc')
|
|
|
|
SimObject('ArmNativeTrace.py')
|
|
SimObject('ArmTLB.py')
|
|
|
|
TraceFlag('Arm')
|
|
TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
|
|
if env['FULL_SYSTEM']:
|
|
#Insert Full-System Files Here
|
|
pass
|
|
else:
|
|
Source('process.cc')
|
|
Source('linux/linux.cc')
|
|
Source('linux/process.cc')
|
|
|
|
# Add in files generated by the ISA description.
|
|
isa_desc_files = env.ISADesc('isa/main.isa')
|
|
# Only non-header files need to be compiled.
|
|
for f in isa_desc_files:
|
|
if not f.path.endswith('.hh'):
|
|
Source(f)
|
|
|