gem5/src
Mitch Hayenga 1716749c8c cpu: Fix o3 front-end pipeline interlock behavior
The o3 pipeline interlock/stall logic is incorrect.  o3 unnecessicarily stalled
fetch and decode due to later stages in the pipeline.  In general, a stage
should usually only consider if it is stalled by the adjacent, downstream stage.
Forcing stalls due to later stages creates and results in bubbles in the
pipeline.  Additionally, o3 stalled the entire frontend (fetch, decode, rename)
on a branch mispredict while the ROB is being serially walked to update the
RAT (robSquashing). Only should have stalled at rename.
2014-09-03 07:42:34 -04:00
..
arch arch: Properly guess OpClass from optional StaticInst flags 2014-09-03 07:42:32 -04:00
base base: Add const to intmath and be more flexible with typing 2014-08-26 10:14:32 -04:00
cpu cpu: Fix o3 front-end pipeline interlock behavior 2014-09-03 07:42:34 -04:00
dev dev: Avoid invalid sized reads in PL390 with DPRINTF enabled 2014-09-03 07:42:27 -04:00
doc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
kern arch: Cleanup unused ISA traits constants 2014-09-03 07:42:21 -04:00
mem cache: Fix handling of LL/SC requests under contention 2014-09-03 07:42:31 -04:00
proto mem: change the namespace Message to ProtoMessage 2014-09-01 16:55:46 -05:00
python config: Change parsing of Addr so hex values work from scripts 2014-09-03 07:42:20 -04:00
sim sim: Fix checkpoint restore for Ticked 2014-09-03 07:42:25 -04:00
unittest unittest: Fix build errors 2014-01-30 12:21:58 -06:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript scons: Silence clang 3.4 warnings on Ubuntu 12.04 2014-08-13 06:57:28 -04:00