16dcebf4c4
python/m5/objects/BaseCache.mpy:
Add mem_trace parameter.
--HG--
extra : convert_revision : a0bab53fabd7426eee5ca9c845c02a6ac2e1722f
64 lines
3 KiB
Text
64 lines
3 KiB
Text
from BaseMem import BaseMem
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class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
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simobj BaseCache(BaseMem):
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type = 'BaseCache'
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adaptive_compression = Param.Bool(False,
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"Use an adaptive compression scheme")
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assoc = Param.Int("associativity")
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block_size = Param.Int("block size in bytes")
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compressed_bus = Param.Bool(False,
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"This cache connects to a compressed memory")
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compression_latency = Param.Latency('0c',
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"Latency in cycles of compression algorithm")
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do_copy = Param.Bool(False, "perform fast copies in the cache")
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hash_delay = Param.Int(1, "time in cycles of hash access")
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in_bus = Param.Bus(NULL, "incoming bus object")
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lifo = Param.Bool(False,
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"whether this NIC partition should use LIFO repl. policy")
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max_miss_count = Param.Counter(0,
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"number of misses to handle before calling exit")
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mem_trace = Param.MemTraceWriter(NULL,
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"memory trace writer to record accesses")
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mshrs = Param.Int("number of MSHRs (max outstanding requests)")
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out_bus = Param.Bus("outgoing bus object")
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prioritizeRequests = Param.Bool(False,
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"always service demand misses first")
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protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
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repl = Param.Repl(NULL, "replacement policy")
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size = Param.MemorySize("capacity in bytes")
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split = Param.Bool(False, "whether or not this cache is split")
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split_size = Param.Int(0,
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"How many ways of the cache belong to CPU/LRU partition")
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store_compressed = Param.Bool(False,
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"Store compressed data in the cache")
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subblock_size = Param.Int(0,
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"Size of subblock in IIC used for compression")
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tgts_per_mshr = Param.Int("max number of accesses per MSHR")
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trace_addr = Param.Addr(0, "address to trace")
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two_queue = Param.Bool(False,
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"whether the lifo should have two queue replacement")
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write_buffers = Param.Int(8, "number of write buffers")
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prefetch_miss = Param.Bool(False,
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"wheter you are using the hardware prefetcher from Miss stream")
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prefetch_access = Param.Bool(False,
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"wheter you are using the hardware prefetcher from Access stream")
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prefetcher_size = Param.Int(100,
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"Number of entries in the harware prefetch queue")
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prefetch_past_page = Param.Bool(False,
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"Allow prefetches to cross virtual page boundaries")
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prefetch_serial_squash = Param.Bool(False,
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"Squash prefetches with a later time on a subsequent miss")
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prefetch_degree = Param.Int(1,
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"Degree of the prefetch depth")
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prefetch_latency = Param.Tick(10,
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"Latency of the prefetcher")
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prefetch_policy = Param.Prefetch('none',
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"Type of prefetcher to use")
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prefetch_cache_check_push = Param.Bool(True,
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"Check if in cash on push or pop of prefetch queue")
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prefetch_use_cpu_id = Param.Bool(True,
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"Use the CPU ID to seperate calculations of prefetches")
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prefetch_data_accesses_only = Param.Bool(False,
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"Only prefetch on data not on instruction accesses")
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