10c79efe55
SConscript: The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away. arch/alpha/alpha_memory.cc: Changed Fault to Fault * and took the underscores out of fault names. arch/alpha/alpha_memory.hh: Changed Fault to Fault *. Also, added an include for the alpha faults. arch/alpha/ev5.cc: Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names. arch/alpha/isa/decoder.isa: Changed Fault to Fault * and took the underscores out fault names. arch/alpha/isa/fp.isa: Changed Fault to Fault *, and took the underscores out of fault names. arch/alpha/isa/main.isa: Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files. arch/alpha/isa/mem.isa: Changed Fault to Fault * and removed underscores from fault names. arch/alpha/isa/unimp.isa: arch/alpha/isa/unknown.isa: cpu/exec_context.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: dev/alpha_console.cc: dev/ide_ctrl.cc: dev/isa_fake.cc: dev/pciconfigall.cc: dev/pcidev.cc: dev/pcidev.hh: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Changed Fault to Fault *, and removed underscores from fault names. arch/alpha/isa_traits.hh: Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed. cpu/base_dyn_inst.cc: Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault. cpu/base_dyn_inst.hh: Changed Fault to Fault * and took the underscores out of the fault names. cpu/exec_context.cc: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_dyn_inst_impl.hh: cpu/o3/fetch.hh: dev/alpha_console.hh: dev/baddev.hh: dev/ide_ctrl.hh: dev/isa_fake.hh: dev/ns_gige.hh: dev/pciconfigall.hh: dev/sinic.hh: dev/tsunami_cchip.hh: dev/tsunami_io.hh: dev/tsunami_pchip.hh: dev/uart.hh: dev/uart8250.hh: Changed Fault to Fault *. cpu/o3/alpha_cpu.hh: Changed Fault to Fault *, removed underscores from fault names. cpu/o3/alpha_cpu_impl.hh: Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away. cpu/o3/commit_impl.hh: cpu/o3/fetch_impl.hh: dev/baddev.cc: Changed Fault to Fault *, and removed underscores from the fault names. cpu/o3/regfile.hh: Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names. cpu/simple/cpu.hh: Changed Fault to Fault * dev/ns_gige.cc: Changed Fault to Fault *, and removdd underscores from fault names. dev/sinic.cc: Changed Fault to Fault *, and removed the underscores from fault names. dev/uart8250.cc: Chanted Fault to Fault *, and removed underscores from fault names. kern/kernel_stats.cc: Removed underscores from fault names, and from NumFaults. kern/kernel_stats.hh: Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally. sim/faults.cc: This allocates the system wide faults. sim/faults.hh: This declares the system wide faults. sim/syscall_emul.cc: sim/syscall_emul.hh: Removed the underscores from fault names. --HG-- rename : arch/alpha/faults.cc => sim/faults.cc rename : arch/alpha/faults.hh => sim/faults.hh extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
363 lines
9.6 KiB
C++
363 lines
9.6 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_BASE_DYN_INST_CC__
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#define __CPU_BASE_DYN_INST_CC__
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#include <iostream>
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#include <string>
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#include <sstream>
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#include "base/cprintf.hh"
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#include "base/trace.hh"
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#include "arch/alpha/faults.hh"
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#include "cpu/exetrace.hh"
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#include "mem/mem_req.hh"
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#include "cpu/base_dyn_inst.hh"
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#include "cpu/o3/alpha_impl.hh"
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#include "cpu/o3/alpha_cpu.hh"
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using namespace std;
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#define NOHASH
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#ifndef NOHASH
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#include "base/hashmap.hh"
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unsigned int MyHashFunc(const BaseDynInst *addr)
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{
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unsigned a = (unsigned)addr;
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unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
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return hash;
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}
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typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc> my_hash_t;
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my_hash_t thishash;
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#endif
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template <class Impl>
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BaseDynInst<Impl>::BaseDynInst(MachInst machInst, Addr inst_PC,
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Addr pred_PC, InstSeqNum seq_num,
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FullCPU *cpu)
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: staticInst(machInst), traceData(NULL), cpu(cpu), xc(cpu->xcBase())
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{
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seqNum = seq_num;
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PC = inst_PC;
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nextPC = PC + sizeof(MachInst);
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predPC = pred_PC;
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initVars();
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}
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template <class Impl>
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BaseDynInst<Impl>::BaseDynInst(StaticInstPtr<ISA> &_staticInst)
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: staticInst(_staticInst), traceData(NULL)
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{
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initVars();
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}
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template <class Impl>
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void
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BaseDynInst<Impl>::initVars()
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{
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effAddr = MemReq::inval_addr;
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physEffAddr = MemReq::inval_addr;
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readyRegs = 0;
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completed = false;
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canIssue = false;
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issued = false;
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executed = false;
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canCommit = false;
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squashed = false;
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squashedInIQ = false;
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eaCalcDone = false;
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blockingInst = false;
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recoverInst = false;
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// Eventually make this a parameter.
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threadNumber = 0;
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// Also make this a parameter, or perhaps get it from xc or cpu.
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asid = 0;
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// Initialize the fault to be unimplemented opcode.
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fault = UnimplementedOpcodeFault;
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++instcount;
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DPRINTF(FullCPU, "DynInst: Instruction created. Instcount=%i\n",
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instcount);
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}
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template <class Impl>
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BaseDynInst<Impl>::~BaseDynInst()
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{
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--instcount;
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DPRINTF(FullCPU, "DynInst: Instruction destroyed. Instcount=%i\n",
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instcount);
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}
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template <class Impl>
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void
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BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
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{
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// This is the "functional" implementation of prefetch. Not much
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// happens here since prefetches don't affect the architectural
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// state.
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// Generate a MemReq so we can translate the effective address.
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MemReqPtr req = new MemReq(addr, xc, 1, flags);
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req->asid = asid;
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// Prefetches never cause faults.
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fault = NoFault;
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// note this is a local, not BaseDynInst::fault
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Fault * trans_fault = xc->translateDataReadReq(req);
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if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
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// It's a valid address to cacheable space. Record key MemReq
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// parameters so we can generate another one just like it for
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// the timing access without calling translate() again (which
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// might mess up the TLB).
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effAddr = req->vaddr;
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physEffAddr = req->paddr;
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memReqFlags = req->flags;
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} else {
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// Bogus address (invalid or uncacheable space). Mark it by
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// setting the eff_addr to InvalidAddr.
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effAddr = physEffAddr = MemReq::inval_addr;
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}
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/**
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* @todo
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* Replace the disjoint functional memory with a unified one and remove
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* this hack.
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*/
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#if !FULL_SYSTEM
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req->paddr = req->vaddr;
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#endif
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if (traceData) {
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traceData->setAddr(addr);
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}
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}
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template <class Impl>
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void
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BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
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{
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// Need to create a MemReq here so we can do a translation. This
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// will casue a TLB miss trap if necessary... not sure whether
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// that's the best thing to do or not. We don't really need the
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// MemReq otherwise, since wh64 has no functional effect.
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MemReqPtr req = new MemReq(addr, xc, size, flags);
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req->asid = asid;
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fault = xc->translateDataWriteReq(req);
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if (fault == NoFault && !(req->flags & UNCACHEABLE)) {
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// Record key MemReq parameters so we can generate another one
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// just like it for the timing access without calling translate()
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// again (which might mess up the TLB).
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effAddr = req->vaddr;
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physEffAddr = req->paddr;
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memReqFlags = req->flags;
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} else {
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// ignore faults & accesses to uncacheable space... treat as no-op
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effAddr = physEffAddr = MemReq::inval_addr;
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}
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storeSize = size;
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storeData = 0;
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}
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/**
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* @todo Need to find a way to get the cache block size here.
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*/
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template <class Impl>
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Fault *
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BaseDynInst<Impl>::copySrcTranslate(Addr src)
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{
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MemReqPtr req = new MemReq(src, xc, 64);
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req->asid = asid;
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// translate to physical address
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Fault * fault = xc->translateDataReadReq(req);
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if (fault == NoFault) {
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xc->copySrcAddr = src;
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xc->copySrcPhysAddr = req->paddr;
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} else {
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xc->copySrcAddr = 0;
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xc->copySrcPhysAddr = 0;
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}
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return fault;
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}
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/**
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* @todo Need to find a way to get the cache block size here.
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*/
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template <class Impl>
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Fault *
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BaseDynInst<Impl>::copy(Addr dest)
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{
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uint8_t data[64];
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FunctionalMemory *mem = xc->mem;
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assert(xc->copySrcPhysAddr || xc->misspeculating());
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MemReqPtr req = new MemReq(dest, xc, 64);
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req->asid = asid;
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// translate to physical address
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Fault * fault = xc->translateDataWriteReq(req);
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if (fault == NoFault) {
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Addr dest_addr = req->paddr;
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// Need to read straight from memory since we have more than 8 bytes.
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req->paddr = xc->copySrcPhysAddr;
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mem->read(req, data);
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req->paddr = dest_addr;
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mem->write(req, data);
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}
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return fault;
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}
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template <class Impl>
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void
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BaseDynInst<Impl>::dump()
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{
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cprintf("T%d : %#08d `", threadNumber, PC);
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cout << staticInst->disassemble(PC);
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cprintf("'\n");
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}
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template <class Impl>
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void
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BaseDynInst<Impl>::dump(std::string &outstring)
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{
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std::ostringstream s;
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s << "T" << threadNumber << " : 0x" << PC << " "
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<< staticInst->disassemble(PC);
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outstring = s.str();
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}
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#if 0
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template <class Impl>
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Fault *
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BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
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{
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Fault * fault;
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// check alignments, even speculative this test should always pass
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if ((nbytes & nbytes - 1) != 0 || (addr & nbytes - 1) != 0) {
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for (int i = 0; i < nbytes; i++)
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((char *) p)[i] = 0;
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// I added the following because according to the comment above,
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// we should never get here. The comment lies
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#if 0
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panic("unaligned access. Cycle = %n", curTick);
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#endif
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return NoFault;
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}
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MemReqPtr req = new MemReq(addr, thread, nbytes);
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switch(cmd) {
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case Read:
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fault = spec_mem->read(req, (uint8_t *)p);
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break;
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case Write:
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fault = spec_mem->write(req, (uint8_t *)p);
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if (fault != NoFault)
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break;
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specMemWrite = true;
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storeSize = nbytes;
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switch(nbytes) {
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case sizeof(uint8_t):
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*(uint8_t)&storeData = (uint8_t *)p;
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break;
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case sizeof(uint16_t):
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*(uint16_t)&storeData = (uint16_t *)p;
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break;
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case sizeof(uint32_t):
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*(uint32_t)&storeData = (uint32_t *)p;
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break;
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case sizeof(uint64_t):
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*(uint64_t)&storeData = (uint64_t *)p;
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break;
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}
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break;
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default:
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fault = MachineCheckFault;
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break;
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}
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trace_mem(fault, cmd, addr, p, nbytes);
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return fault;
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}
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#endif
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template <class Impl>
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bool
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BaseDynInst<Impl>::eaSrcsReady()
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{
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// For now I am assuming that src registers 1..n-1 are the ones that the
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// EA calc depends on. (i.e. src reg 0 is the source of the data to be
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// stored)
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for (int i = 1; i < numSrcRegs(); ++i)
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{
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if (!_readySrcRegIdx[i])
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return false;
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}
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return true;
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}
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// Forward declaration
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template class BaseDynInst<AlphaSimpleImpl>;
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template <>
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int
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BaseDynInst<AlphaSimpleImpl>::instcount = 0;
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#endif // __CPU_BASE_DYN_INST_CC__
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