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gem5/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
Steve Reinhardt 1483496803 stats: update Minor stats due to PF bug fix 
A recent changeset of mine (http://repo.gem5.org/gem5/rev/4cfe55719da5)
inadvertently fixed a bug in the Minor CPU model which caused it to treat
software prefetches as regular loads.  Prior to this changeset, Minor
did an ad-hoc generation of memory commands that left out the PF check;
because it now uses the common code that the other CPU models use,
it generates prefetches properly.  These stat changes reflect the fact
that the Minor model now issues SoftPFReqs.
2015-03-19 08:41:32 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 0.545057 # Number of seconds simulated
sim_ticks 545056655500 # Number of ticks simulated
final_tick 545056655500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 122221 # Simulator instruction rate (inst/s)
host_op_rate 150470 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 103982941 # Simulator tick rate (ticks/s)
host_mem_usage 247272 # Number of bytes of host memory used
host_seconds 5241.79 # Real time elapsed on the host
sim_insts 640655084 # Number of instructions simulated
sim_ops 788730743 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 164864 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18429248 # Number of bytes read from this memory
system.physmem.bytes_read::total 18594112 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 164864 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 164864 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2576 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 287957 # Number of read requests responded to by this memory
system.physmem.num_reads::total 290533 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 302471 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 33811619 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 34114090 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 302471 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 302471 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 7761160 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 7761160 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 7761160 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 302471 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 33811619 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 41875251 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 290533 # Number of read requests accepted
system.physmem.writeReqs 66098 # Number of write requests accepted
system.physmem.readBursts 290533 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 18574784 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue
system.physmem.bytesWritten 4228736 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 18594112 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 18287 # Per bank write bursts
system.physmem.perBankRdBursts::1 18141 # Per bank write bursts
system.physmem.perBankRdBursts::2 18224 # Per bank write bursts
system.physmem.perBankRdBursts::3 18184 # Per bank write bursts
system.physmem.perBankRdBursts::4 18267 # Per bank write bursts
system.physmem.perBankRdBursts::5 18318 # Per bank write bursts
system.physmem.perBankRdBursts::6 18100 # Per bank write bursts
system.physmem.perBankRdBursts::7 17916 # Per bank write bursts
system.physmem.perBankRdBursts::8 17940 # Per bank write bursts
system.physmem.perBankRdBursts::9 17966 # Per bank write bursts
system.physmem.perBankRdBursts::10 18025 # Per bank write bursts
system.physmem.perBankRdBursts::11 18111 # Per bank write bursts
system.physmem.perBankRdBursts::12 18143 # Per bank write bursts
system.physmem.perBankRdBursts::13 18269 # Per bank write bursts
system.physmem.perBankRdBursts::14 18078 # Per bank write bursts
system.physmem.perBankRdBursts::15 18262 # Per bank write bursts
system.physmem.perBankWrBursts::0 4173 # Per bank write bursts
system.physmem.perBankWrBursts::1 4099 # Per bank write bursts
system.physmem.perBankWrBursts::2 4136 # Per bank write bursts
system.physmem.perBankWrBursts::3 4146 # Per bank write bursts
system.physmem.perBankWrBursts::4 4225 # Per bank write bursts
system.physmem.perBankWrBursts::5 4223 # Per bank write bursts
system.physmem.perBankWrBursts::6 4171 # Per bank write bursts
system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
system.physmem.perBankWrBursts::8 4094 # Per bank write bursts
system.physmem.perBankWrBursts::9 4093 # Per bank write bursts
system.physmem.perBankWrBursts::10 4093 # Per bank write bursts
system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
system.physmem.perBankWrBursts::15 4140 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 545056561000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 290533 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 66098 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 289840 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 375 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 966 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 966 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4010 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4010 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4010 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4010 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4010 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 4011 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 4009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 4009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 4009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 4009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 4009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 4009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 4009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 4009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 112303 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 203.039278 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 132.213865 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 254.441282 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 47271 42.09% 42.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 43737 38.95% 81.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 8997 8.01% 89.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 1907 1.70% 90.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 490 0.44% 91.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 737 0.66% 91.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 726 0.65% 92.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 505 0.45% 92.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7933 7.06% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 112303 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 48.526066 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 36.050433 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 507.549530 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.481417 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.460113 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.855134 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 3044 75.93% 75.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 965 24.07% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads
system.physmem.totQLat 2738025750 # Total ticks spent queuing
system.physmem.totMemAccLat 8179857000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1451155000 # Total ticks spent in databus transfers
system.physmem.avgQLat 9433.95 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 28183.95 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 34.08 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 7.76 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 34.11 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 7.76 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.33 # Data bus utilization in percentage
system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing
system.physmem.readRowHits 193900 # Number of row buffer hits during reads
system.physmem.writeRowHits 50093 # Number of row buffer hits during writes
system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes
system.physmem.avgGap 1528348.80 # Average gap between requests
system.physmem.pageHitRate 68.47 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 424055520 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 231379500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1134369600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 215570160 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 106906564890 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 233254311000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 377766467790 # Total energy per rank (pJ)
system.physmem_0.averagePower 693.081659 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 387327017750 # Time in different power states
system.physmem_0.memoryStateTime::REF 18200520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 139526544250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 424894680 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 231837375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1129096800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 105911923725 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 234126803250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 377637362310 # Total energy per rank (pJ)
system.physmem_1.averagePower 692.844791 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 388779883250 # Time in different power states
system.physmem_1.memoryStateTime::REF 18200520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 138072943000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 155213668 # Number of BP lookups
system.cpu.branchPred.condPredicted 105449696 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 12879317 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 90304208 # Number of BTB lookups
system.cpu.branchPred.BTBHits 82854286 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 91.750194 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 19341274 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls
system.cpu.numCycles 1090113311 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 640655084 # Number of instructions committed
system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed
system.cpu.discardedOps 22623250 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.701560 # CPI: cycles per instruction
system.cpu.ipc 0.587696 # IPC: instructions per cycle
system.cpu.tickCycles 1030410775 # Number of cycles that the object actually ticked
system.cpu.idleCycles 59702536 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 778141 # number of replacements
system.cpu.dcache.tags.tagsinuse 4092.460106 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 378456342 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 782237 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 483.812888 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 802330000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.460106 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999136 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999136 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 963 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1339 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1594 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 759397955 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 759397955 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 249627614 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 249627614 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 3485 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 3485 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 378441379 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 378441379 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 378444864 # number of overall hits
system.cpu.dcache.overall_hits::total 378444864 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 713664 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 713664 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 851376 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 851376 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 851517 # number of overall misses
system.cpu.dcache.overall_misses::total 851517 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 24697977718 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 24697977718 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10190251750 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10190251750 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 34888229468 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 34888229468 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 34888229468 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 34888229468 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 250341278 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 250341278 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3626 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 3626 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 379292755 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 379292755 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 379296381 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 379296381 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002851 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038886 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.038886 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34607.290991 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34607.290991 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73996.832157 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73996.832157 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40978.638660 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 40978.638660 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40971.853137 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 40971.853137 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks
system.cpu.dcache.writebacks::total 91420 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 888 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 888 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 69278 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 69278 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 69278 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 69278 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712776 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 712776 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 782098 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 782098 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 782237 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 782237 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23542622277 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23542622277 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5045531250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5045531250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1719000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1719000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28588153527 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 28588153527 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28589872527 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 28589872527 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038334 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038334 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33029.482302 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33029.482302 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72783.982718 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72783.982718 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.906475 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.906475 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36553.160252 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 36553.160252 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36548.862464 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 36548.862464 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 23596 # number of replacements
system.cpu.icache.tags.tagsinuse 1712.064970 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 291953853 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 11518.280388 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1712.064970 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.835969 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.835969 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1600 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 583983749 # Number of tag accesses
system.cpu.icache.tags.data_accesses 583983749 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 291953853 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 291953853 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 291953853 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 291953853 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 291953853 # number of overall hits
system.cpu.icache.overall_hits::total 291953853 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses
system.cpu.icache.overall_misses::total 25348 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 499948995 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 499948995 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 499948995 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 499948995 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 499948995 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 499948995 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 291979201 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 291979201 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 291979201 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 291979201 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 291979201 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 291979201 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19723.409934 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 19723.409934 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19723.409934 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 19723.409934 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19723.409934 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 19723.409934 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25348 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 25348 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 25348 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 460820505 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 460820505 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 460820505 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 460820505 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 460820505 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 460820505 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18179.757969 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18179.757969 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18179.757969 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18179.757969 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18179.757969 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18179.757969 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 257753 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32573.758043 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 538992 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 290497 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 1.855413 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 2882.231572 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.601388 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 29601.925083 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.087959 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002734 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.903379 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.994072 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 287 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2793 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29433 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 7551859 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 7551859 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 22766 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 491022 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 513788 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 91420 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 91420 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 22766 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 494253 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 517019 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 22766 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 494253 # number of overall hits
system.cpu.l2cache.overall_hits::total 517019 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 2582 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 221893 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 224475 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2582 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 287984 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 290566 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2582 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 287984 # number of overall misses
system.cpu.l2cache.overall_misses::total 290566 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 196430000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17675629250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 17872059250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4942281750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4942281750 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 196430000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 22617911000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22814341000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 196430000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 22617911000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22814341000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 25348 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 712915 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 738263 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 25348 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 782237 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 807585 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 25348 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 782237 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 807585 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101862 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311247 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.304058 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101862 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.368154 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.359796 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101862 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.368154 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.359796 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76076.684741 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79658.345464 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 79617.147789 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74779.951128 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74779.951128 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76076.684741 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78538.776460 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 78516.898054 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76076.684741 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78538.776460 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 78516.898054 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 27 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2577 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221866 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 224443 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2577 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 287957 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 290534 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2577 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 287957 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 290534 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163824250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14898374500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15062198750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4113937750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4113937750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163824250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19012312250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 19176136500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163824250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19012312250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 19176136500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311210 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.304015 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368120 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.359757 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368120 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.359757 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63571.691890 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67150.327225 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67109.238203 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62246.565342 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62246.565342 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63571.691890 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66024.830964 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66003.071930 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63571.691890 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66024.830964 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66003.071930 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 738263 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 738262 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655894 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1706589 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55914048 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 57536256 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 899005 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 899005 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 899005 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 540922500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 38574495 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1224002973 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.trans_dist::ReadReq 224442 # Transaction distribution
system.membus.trans_dist::ReadResp 224442 # Transaction distribution
system.membus.trans_dist::Writeback 66098 # Transaction distribution
system.membus.trans_dist::ReadExReq 66091 # Transaction distribution
system.membus.trans_dist::ReadExResp 66091 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647164 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 647164 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824384 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22824384 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 356631 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 356631 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 356631 # Request fanout histogram
system.membus.reqLayer0.occupancy 731518000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 1551221500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
---------- End Simulation Statistics ----------
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