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gem5/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
Steve Reinhardt 1483496803 stats: update Minor stats due to PF bug fix 
A recent changeset of mine (http://repo.gem5.org/gem5/rev/4cfe55719da5)
inadvertently fixed a bug in the Minor CPU model which caused it to treat
software prefetches as regular loads.  Prior to this changeset, Minor
did an ad-hoc generation of memory commands that left out the PF check;
because it now uses the common code that the other CPU models use,
it generates prefetches properly.  These stat changes reflect the fact
that the Minor model now issues SoftPFReqs.
2015-03-19 08:41:32 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 0.061589 # Number of seconds simulated
sim_ticks 61589191500 # Number of ticks simulated
final_tick 61589191500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 169101 # Simulator instruction rate (inst/s)
host_op_rate 169943 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 114949938 # Simulator tick rate (ticks/s)
host_mem_usage 374724 # Number of bytes of host memory used
host_seconds 535.79 # Real time elapsed on the host
sim_insts 90602849 # Number of instructions simulated
sim_ops 91054080 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 49600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory
system.physmem.bytes_read::total 996800 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 775 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 805336 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 15379322 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 16184658 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 805336 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 805336 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 805336 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 15379322 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 16184658 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15575 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 996800 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 996800 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 993 # Per bank write bursts
system.physmem.perBankRdBursts::1 890 # Per bank write bursts
system.physmem.perBankRdBursts::2 949 # Per bank write bursts
system.physmem.perBankRdBursts::3 1028 # Per bank write bursts
system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
system.physmem.perBankRdBursts::5 1113 # Per bank write bursts
system.physmem.perBankRdBursts::6 1088 # Per bank write bursts
system.physmem.perBankRdBursts::7 1088 # Per bank write bursts
system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
system.physmem.perBankRdBursts::9 962 # Per bank write bursts
system.physmem.perBankRdBursts::10 938 # Per bank write bursts
system.physmem.perBankRdBursts::11 899 # Per bank write bursts
system.physmem.perBankRdBursts::12 904 # Per bank write bursts
system.physmem.perBankRdBursts::13 867 # Per bank write bursts
system.physmem.perBankRdBursts::14 877 # Per bank write bursts
system.physmem.perBankRdBursts::15 905 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 61589097000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 15575 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1548 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 642.728682 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 437.613794 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 401.141843 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 250 16.15% 16.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 184 11.89% 28.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 91 5.88% 33.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 69 4.46% 38.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 77 4.97% 43.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 93 6.01% 49.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 43 2.78% 52.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 36 2.33% 54.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 705 45.54% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1548 # Bytes accessed per row activation
system.physmem.totQLat 76265750 # Total ticks spent queuing
system.physmem.totMemAccLat 368297000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers
system.physmem.avgQLat 4896.68 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 23646.68 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.13 # Data bus utilization in percentage
system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 14017 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.00 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 3954356.15 # Average gap between requests
system.physmem.pageHitRate 90.00 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 6365520 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3473250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 63663600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 4022201040 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2552305815 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 34710162000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 41358171225 # Total energy per rank (pJ)
system.physmem_0.averagePower 671.598278 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 57736612750 # Time in different power states
system.physmem_0.memoryStateTime::REF 2056340000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1792195250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 5322240 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2904000 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 4022201040 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2572075980 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 34692811500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 41352777360 # Total energy per rank (pJ)
system.physmem_1.averagePower 671.510839 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 57709022500 # Time in different power states
system.physmem_1.memoryStateTime::REF 2056340000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1820633500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 20789992 # Number of BP lookups
system.cpu.branchPred.condPredicted 17092121 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 765794 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 8976081 # Number of BTB lookups
system.cpu.branchPred.BTBHits 8866607 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 98.780381 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 62695 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 123178383 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90602849 # Number of instructions committed
system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2068275 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.359542 # CPI: cycles per instruction
system.cpu.ipc 0.735542 # IPC: instructions per cycle
system.cpu.tickCycles 109824698 # Number of cycles that the object actually ticked
system.cpu.idleCycles 13353685 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 946107 # number of replacements
system.cpu.dcache.tags.tagsinuse 3616.117477 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26267654 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 27.644255 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 20661192250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3616.117477 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.882841 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.882841 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2243 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1593 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 55463725 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 55463725 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 21598560 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21598560 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4660812 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4660812 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 26259372 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26259372 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26259880 # number of overall hits
system.cpu.dcache.overall_hits::total 26259880 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 914934 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 914934 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 74169 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 74169 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 989103 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 989103 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 989107 # number of overall misses
system.cpu.dcache.overall_misses::total 989107 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918328994 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11918328994 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566867500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2566867500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 14485196494 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14485196494 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14485196494 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14485196494 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22513494 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22513494 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 27248475 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 27248475 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 27248987 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27248987 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015664 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015664 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.036299 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.036299 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.435780 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.435780 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34608.360636 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34608.360636 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14644.780669 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14644.780669 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.721445 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14644.721445 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 943285 # number of writebacks
system.cpu.dcache.writebacks::total 943285 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11501 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 11501 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27402 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 27402 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 38903 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 38903 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 38903 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 38903 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903433 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 903433 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46767 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46767 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 950200 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 950200 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 950203 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10413180006 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10413180006 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1463830500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1463830500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 155500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 155500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11877010506 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11877010506 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877166006 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11877166006 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040129 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040129 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.233828 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.233828 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31300.500353 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31300.500353 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51833.333333 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51833.333333 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.484852 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.484852 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.609037 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.609037 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 5 # number of replacements
system.cpu.icache.tags.tagsinuse 690.367878 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 27855563 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 34689.368618 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 690.367878 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.337094 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.337094 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 55713535 # Number of tag accesses
system.cpu.icache.tags.data_accesses 55713535 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 27855563 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 27855563 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 27855563 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 27855563 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 27855563 # number of overall hits
system.cpu.icache.overall_hits::total 27855563 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses
system.cpu.icache.overall_misses::total 803 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 60778747 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 60778747 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 60778747 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 60778747 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 60778747 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 60778747 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 27856366 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 27856366 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 27856366 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 27856366 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 27856366 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 27856366 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75689.597758 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 75689.597758 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75689.597758 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 75689.597758 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75689.597758 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 75689.597758 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 803 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59238753 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 59238753 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59238753 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 59238753 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59238753 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 59238753 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73771.797011 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73771.797011 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73771.797011 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 73771.797011 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73771.797011 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 73771.797011 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 10238.331530 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1831333 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 117.710053 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 9347.552494 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.372759 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 215.406276 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.285265 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020611 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006574 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.312449 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 15216653 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15216653 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 903174 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 903199 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 943285 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 943285 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 32223 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 32223 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 935397 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 935422 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 935397 # number of overall hits
system.cpu.l2cache.overall_hits::total 935422 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 778 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 262 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1040 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 778 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 15584 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 778 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses
system.cpu.l2cache.overall_misses::total 15584 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58173250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22267000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 80440250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073291000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1073291000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 58173250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1095558000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1153731250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 58173250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1095558000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1153731250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 803 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 903436 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 904239 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 943285 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 943285 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46767 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 46767 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 803 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 950203 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 803 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 950203 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968867 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.001150 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310989 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.310989 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968867 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016387 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968867 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016387 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74772.814910 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84988.549618 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 77346.394231 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73796.135864 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73796.135864 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74772.814910 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73994.191544 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74033.062757 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74772.814910 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73994.191544 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74033.062757 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1031 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48299750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18668000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 66967750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891481000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891481000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48299750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910149000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 958448750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48299750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910149000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 958448750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310989 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310989 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62322.258065 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72921.875000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64954.170708 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61295.448295 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61295.448295 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62322.258065 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61496.554054 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61537.640449 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62322.258065 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61496.554054 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61537.640449 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 904239 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 904239 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 943285 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 46767 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 46767 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843691 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2845297 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183232 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 121234624 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 1894291 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 1894291 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1894291 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 1890430500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1372247 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1428681994 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
system.membus.trans_dist::ReadReq 1031 # Transaction distribution
system.membus.trans_dist::ReadResp 1031 # Transaction distribution
system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 996800 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 15575 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 15575 # Request fanout histogram
system.membus.reqLayer0.occupancy 21630500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 82148250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
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