041ea8107e
This patch breaks out the cache write buffer into a separate class, without affecting any stats. The goal of the patch is to avoid encumbering the much-simpler write queue with the complex MSHR handling. In a follow on patch this simplification allows us to implement write combining. The WriteQueue gets its own class, but shares a common ancestor, the generic Queue, with the MSHRQueue.
98 lines
3.9 KiB
C++
98 lines
3.9 KiB
C++
/*
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* Copyright (c) 2015-2016 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Hansson
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*/
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/**
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* @file Declaration of a queue structure to manage uncacheable write
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* and writebacks.
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*/
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#ifndef __MEM_CACHE_WRITE_QUEUE_HH__
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#define __MEM_CACHE_WRITE_QUEUE_HH__
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#include <vector>
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#include "mem/cache/queue.hh"
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#include "mem/cache/write_queue_entry.hh"
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/**
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* A write queue for all eviction packets, i.e. writebacks and clean
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* evictions, as well as uncacheable writes.
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*/
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class WriteQueue : public Queue<WriteQueueEntry>
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{
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public:
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/**
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* Create a write queue with a given number of entries.
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* @param num_entries The number of entries in this queue.
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* @param reserve The maximum number of entries needed to satisfy
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* any access.
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*/
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WriteQueue(const std::string &_label, int num_entries, int reserve);
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/**
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* Allocates a new WriteQueueEntry for the request and size. This
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* places the request as the first target in the WriteQueueEntry.
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*
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* @param blk_addr The address of the block.
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* @param blk_size The number of bytes to request.
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* @param pkt The original write.
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* @param when_ready When is the WriteQueueEntry be ready to act upon.
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* @param order The logical order of this WriteQueueEntry
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*
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* @return The a pointer to the WriteQueueEntry allocated.
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*
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* @pre There are free entries.
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*/
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WriteQueueEntry *allocate(Addr blk_addr, unsigned blk_size,
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PacketPtr pkt, Tick when_ready, Counter order);
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/**
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* Mark the given entry as in service. This removes the entry from
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* the readyList or deallocates the entry if it does not expect a
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* response (writeback/eviction rather than an uncacheable write).
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*
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* @param entry The entry to mark in service.
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*/
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void markInService(WriteQueueEntry *entry);
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};
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#endif //__MEM_CACHE_WRITE_QUEUE_HH__
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