ce2722cdd9
If the cache access mode is parallel, i.e. "sequential_access" parameter is set to "False", tags and data are accessed in parallel. Therefore, the hit_latency is the maximum latency between tag_latency and data_latency. On the other hand, if the cache access mode is sequential, i.e. "sequential_access" parameter is set to "True", tags and data are accessed sequentially. Therefore, the hit_latency is the sum of tag_latency plus data_latency. Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
336 lines
9.9 KiB
C++
336 lines
9.9 KiB
C++
/*
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* Copyright (c) 2012-2013 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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*/
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/**
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* @file
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* Declaration of a fully associative LRU tag store.
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*/
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#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__
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#define __MEM_CACHE_TAGS_FA_LRU_HH__
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#include <list>
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#include <unordered_map>
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#include "mem/cache/base.hh"
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#include "mem/cache/blk.hh"
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#include "mem/cache/tags/base.hh"
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#include "mem/packet.hh"
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#include "params/FALRU.hh"
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/**
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* A fully associative cache block.
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*/
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class FALRUBlk : public CacheBlk
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{
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public:
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/** The previous block in LRU order. */
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FALRUBlk *prev;
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/** The next block in LRU order. */
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FALRUBlk *next;
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/** Has this block been touched? */
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bool isTouched;
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/**
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* A bit mask of the sizes of cache that this block is resident in.
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* Each bit represents a power of 2 in MB size cache.
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* If bit 0 is set, this block is in a 1MB cache
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* If bit 2 is set, this block is in a 4MB cache, etc.
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* There is one bit for each cache smaller than the full size (default
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* 16MB).
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*/
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int inCache;
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};
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/**
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* A fully associative LRU cache. Keeps statistics for accesses to a number of
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* cache sizes at once.
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*/
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class FALRU : public BaseTags
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{
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public:
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/** Typedef the block type used in this class. */
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typedef FALRUBlk BlkType;
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/** Typedef a list of pointers to the local block type. */
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typedef std::list<FALRUBlk*> BlkList;
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protected:
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/** Array of pointers to blocks at the cache size boundaries. */
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FALRUBlk **cacheBoundaries;
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/** A mask for the FALRUBlk::inCache bits. */
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int cacheMask;
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/** The number of different size caches being tracked. */
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unsigned numCaches;
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/** The cache blocks. */
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FALRUBlk *blks;
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/** The MRU block. */
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FALRUBlk *head;
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/** The LRU block. */
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FALRUBlk *tail;
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/** Hash table type mapping addresses to cache block pointers. */
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typedef std::unordered_map<Addr, FALRUBlk *, std::hash<Addr> > hash_t;
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/** Iterator into the address hash table. */
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typedef hash_t::const_iterator tagIterator;
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/** The address hash table. */
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hash_t tagHash;
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/**
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* Find the cache block for the given address.
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* @param addr The address to find.
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* @return The cache block of the address, if any.
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*/
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FALRUBlk * hashLookup(Addr addr) const;
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/**
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* Move a cache block to the MRU position.
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* @param blk The block to promote.
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*/
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void moveToHead(FALRUBlk *blk);
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/**
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* Check to make sure all the cache boundaries are still where they should
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* be. Used for debugging.
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* @return True if everything is correct.
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*/
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bool check();
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/**
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* @defgroup FALRUStats Fully Associative LRU specific statistics
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* The FA lru stack lets us track multiple cache sizes at once. These
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* statistics track the hits and misses for different cache sizes.
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* @{
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*/
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/** Hits in each cache size >= 128K. */
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Stats::Vector hits;
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/** Misses in each cache size >= 128K. */
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Stats::Vector misses;
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/** Total number of accesses. */
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Stats::Scalar accesses;
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/**
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* @}
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*/
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public:
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typedef FALRUParams Params;
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/**
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* Construct and initialize this cache tagstore.
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*/
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FALRU(const Params *p);
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~FALRU();
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/**
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* Register the stats for this object.
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* @param name The name to prepend to the stats name.
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*/
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void regStats() override;
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/**
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* Invalidate a cache block.
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* @param blk The block to invalidate.
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*/
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void invalidate(CacheBlk *blk) override;
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/**
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* Access block and update replacement data. May not succeed, in which
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* case nullptr pointer is returned. This has all the implications of a
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* cache access and should only be used as such.
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* Returns the access latency and inCache flags as a side effect.
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* @param addr The address to look for.
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* @param is_secure True if the target memory space is secure.
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* @param asid The address space ID.
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* @param lat The latency of the access.
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* @param inCache The FALRUBlk::inCache flags.
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* @return Pointer to the cache block.
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*/
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CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
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int context_src, int *inCache);
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/**
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* Just a wrapper of above function to conform with the base interface.
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*/
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CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
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int context_src) override;
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/**
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* Find the block in the cache, do not update the replacement data.
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* @param addr The address to look for.
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* @param is_secure True if the target memory space is secure.
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* @param asid The address space ID.
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* @return Pointer to the cache block.
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*/
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CacheBlk* findBlock(Addr addr, bool is_secure) const override;
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/**
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* Find a replacement block for the address provided.
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* @param pkt The request to a find a replacement candidate for.
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* @return The block to place the replacement in.
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*/
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CacheBlk* findVictim(Addr addr) override;
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void insertBlock(PacketPtr pkt, CacheBlk *blk) override;
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/**
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* Return the block size of this cache.
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* @return The block size.
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*/
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unsigned
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getBlockSize() const
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{
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return blkSize;
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}
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/**
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* Return the subblock size of this cache, always the block size.
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* @return The block size.
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*/
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unsigned
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getSubBlockSize() const
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{
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return blkSize;
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}
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/**
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* Return the number of sets this cache has
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* @return The number of sets.
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*/
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unsigned
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getNumSets() const override
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{
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return 1;
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}
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/**
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* Return the number of ways this cache has
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* @return The number of ways.
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*/
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unsigned
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getNumWays() const override
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{
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return numBlocks;
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}
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/**
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* Find the cache block given set and way
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* @param set The set of the block.
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* @param way The way of the block.
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* @return The cache block.
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*/
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CacheBlk* findBlockBySetAndWay(int set, int way) const override;
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/**
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* Align an address to the block size.
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* @param addr the address to align.
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* @return The aligned address.
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*/
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Addr blkAlign(Addr addr) const
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{
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return (addr & ~(Addr)(blkSize-1));
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}
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/**
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* Generate the tag from the addres. For fully associative this is just the
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* block address.
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* @param addr The address to get the tag from.
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* @return The tag.
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*/
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Addr extractTag(Addr addr) const override
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{
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return blkAlign(addr);
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}
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/**
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* Return the set of an address. Only one set in a fully associative cache.
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* @param addr The address to get the set from.
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* @return 0.
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*/
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int extractSet(Addr addr) const override
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{
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return 0;
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}
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/**
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* Regenerate the block address from the tag and the set.
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* @param tag The tag of the block.
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* @param set The set the block belongs to.
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* @return the block address.
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*/
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Addr regenerateBlkAddr(Addr tag, unsigned set) const override
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{
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return (tag);
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}
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/**
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* @todo Implement as in lru. Currently not used
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*/
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virtual std::string print() const override { return ""; }
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/**
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* Visit each block in the tag store and apply a visitor to the
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* block.
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*
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* The visitor should be a function (or object that behaves like a
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* function) that takes a cache block reference as its parameter
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* and returns a bool. A visitor can request the traversal to be
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* stopped by returning false, returning true causes it to be
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* called for the next block in the tag store.
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*
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* \param visitor Visitor to call on each block.
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*/
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void forEachBlk(CacheBlkVisitor &visitor) override {
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for (int i = 0; i < numBlocks; i++) {
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if (!visitor(blks[i]))
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return;
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}
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}
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};
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#endif // __MEM_CACHE_TAGS_FA_LRU_HH__
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