ce2722cdd9
If the cache access mode is parallel, i.e. "sequential_access" parameter is set to "False", tags and data are accessed in parallel. Therefore, the hit_latency is the maximum latency between tag_latency and data_latency. On the other hand, if the cache access mode is sequential, i.e. "sequential_access" parameter is set to "True", tags and data are accessed sequentially. Therefore, the hit_latency is the sum of tag_latency plus data_latency. Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
265 lines
7.7 KiB
C++
265 lines
7.7 KiB
C++
/*
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* Copyright (c) 2012-2014 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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* Ron Dreslinski
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*/
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/**
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* @file
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* Declaration of a common base class for cache tagstore objects.
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*/
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#ifndef __BASE_TAGS_HH__
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#define __BASE_TAGS_HH__
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#include <string>
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#include "base/callback.hh"
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#include "base/statistics.hh"
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#include "mem/cache/blk.hh"
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#include "params/BaseTags.hh"
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#include "sim/clocked_object.hh"
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class BaseCache;
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/**
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* A common base class of Cache tagstore objects.
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*/
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class BaseTags : public ClockedObject
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{
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protected:
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/** The block size of the cache. */
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const unsigned blkSize;
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/** The size of the cache. */
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const unsigned size;
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/** The tag lookup latency of the cache. */
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const Cycles lookupLatency;
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/**
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* The total access latency of the cache. This latency
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* is different depending on the cache access mode
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* (parallel or sequential)
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*/
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const Cycles accessLatency;
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/** Pointer to the parent cache. */
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BaseCache *cache;
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/**
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* The number of tags that need to be touched to meet the warmup
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* percentage.
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*/
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int warmupBound;
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/** Marked true when the cache is warmed up. */
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bool warmedUp;
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/** the number of blocks in the cache */
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unsigned numBlocks;
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// Statistics
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/**
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* @addtogroup CacheStatistics
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* @{
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*/
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/** Number of replacements of valid blocks per thread. */
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Stats::Vector replacements;
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/** Per cycle average of the number of tags that hold valid data. */
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Stats::Average tagsInUse;
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/** The total number of references to a block before it is replaced. */
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Stats::Scalar totalRefs;
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/**
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* The number of reference counts sampled. This is different from
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* replacements because we sample all the valid blocks when the simulator
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* exits.
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*/
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Stats::Scalar sampledRefs;
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/**
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* Average number of references to a block before is was replaced.
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* @todo This should change to an average stat once we have them.
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*/
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Stats::Formula avgRefs;
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/** The cycle that the warmup percentage was hit. */
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Stats::Scalar warmupCycle;
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/** Average occupancy of each requestor using the cache */
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Stats::AverageVector occupancies;
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/** Average occ % of each requestor using the cache */
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Stats::Formula avgOccs;
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/** Occupancy of each context/cpu using the cache */
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Stats::Vector occupanciesTaskId;
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/** Occupancy of each context/cpu using the cache */
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Stats::Vector2d ageTaskId;
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/** Occ % of each context/cpu using the cache */
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Stats::Formula percentOccsTaskId;
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/** Number of tags consulted over all accesses. */
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Stats::Scalar tagAccesses;
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/** Number of data blocks consulted over all accesses. */
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Stats::Scalar dataAccesses;
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/**
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* @}
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*/
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public:
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typedef BaseTagsParams Params;
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BaseTags(const Params *p);
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/**
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* Destructor.
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*/
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virtual ~BaseTags() {}
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/**
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* Set the parent cache back pointer.
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* @param _cache Pointer to parent cache.
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*/
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void setCache(BaseCache *_cache);
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/**
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* Register local statistics.
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*/
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void regStats();
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/**
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* Average in the reference count for valid blocks when the simulation
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* exits.
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*/
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virtual void cleanupRefs() {}
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/**
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* Computes stats just prior to dump event
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*/
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virtual void computeStats() {}
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/**
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* Print all tags used
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*/
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virtual std::string print() const = 0;
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/**
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* Find a block using the memory address
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*/
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virtual CacheBlk * findBlock(Addr addr, bool is_secure) const = 0;
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/**
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* Calculate the block offset of an address.
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* @param addr the address to get the offset of.
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* @return the block offset.
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*/
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int extractBlkOffset(Addr addr) const
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{
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return (addr & (Addr)(blkSize-1));
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}
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/**
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* Find the cache block given set and way
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* @param set The set of the block.
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* @param way The way of the block.
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* @return The cache block.
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*/
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virtual CacheBlk *findBlockBySetAndWay(int set, int way) const = 0;
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/**
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* Limit the allocation for the cache ways.
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* @param ways The maximum number of ways available for replacement.
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*/
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virtual void setWayAllocationMax(int ways)
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{
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panic("This tag class does not implement way allocation limit!\n");
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}
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/**
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* Get the way allocation mask limit.
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* @return The maximum number of ways available for replacement.
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*/
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virtual int getWayAllocationMax() const
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{
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panic("This tag class does not implement way allocation limit!\n");
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return -1;
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}
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virtual unsigned getNumSets() const = 0;
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virtual unsigned getNumWays() const = 0;
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virtual void invalidate(CacheBlk *blk) = 0;
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virtual CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
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int context_src) = 0;
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virtual Addr extractTag(Addr addr) const = 0;
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virtual void insertBlock(PacketPtr pkt, CacheBlk *blk) = 0;
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virtual Addr regenerateBlkAddr(Addr tag, unsigned set) const = 0;
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virtual CacheBlk* findVictim(Addr addr) = 0;
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virtual int extractSet(Addr addr) const = 0;
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virtual void forEachBlk(CacheBlkVisitor &visitor) = 0;
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};
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class BaseTagsCallback : public Callback
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{
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BaseTags *tags;
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public:
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BaseTagsCallback(BaseTags *t) : tags(t) {}
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virtual void process() { tags->cleanupRefs(); };
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};
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class BaseTagsDumpCallback : public Callback
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{
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BaseTags *tags;
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public:
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BaseTagsDumpCallback(BaseTags *t) : tags(t) {}
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virtual void process() { tags->computeStats(); };
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};
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#endif //__BASE_TAGS_HH__
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