ce2722cdd9
If the cache access mode is parallel, i.e. "sequential_access" parameter is set to "False", tags and data are accessed in parallel. Therefore, the hit_latency is the maximum latency between tag_latency and data_latency. On the other hand, if the cache access mode is sequential, i.e. "sequential_access" parameter is set to "True", tags and data are accessed sequentially. Therefore, the hit_latency is the sum of tag_latency plus data_latency. Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
172 lines
5.3 KiB
C++
172 lines
5.3 KiB
C++
/*
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* Copyright (c) 2013 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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* Ron Dreslinski
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*/
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/**
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* @file
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* Definitions of BaseTags.
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*/
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#include "mem/cache/tags/base.hh"
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#include "cpu/smt.hh" //maxThreadsPerCPU
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#include "mem/cache/base.hh"
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#include "sim/sim_exit.hh"
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using namespace std;
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BaseTags::BaseTags(const Params *p)
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: ClockedObject(p), blkSize(p->block_size), size(p->size),
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lookupLatency(p->tag_latency),
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accessLatency(p->sequential_access ?
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p->tag_latency + p->data_latency :
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std::max(p->tag_latency, p->data_latency)),
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cache(nullptr), warmupBound(0),
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warmedUp(false), numBlocks(0)
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{
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}
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void
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BaseTags::setCache(BaseCache *_cache)
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{
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assert(!cache);
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cache = _cache;
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}
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void
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BaseTags::regStats()
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{
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ClockedObject::regStats();
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using namespace Stats;
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replacements
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.init(maxThreadsPerCPU)
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.name(name() + ".replacements")
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.desc("number of replacements")
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.flags(total)
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;
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tagsInUse
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.name(name() + ".tagsinuse")
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.desc("Cycle average of tags in use")
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;
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totalRefs
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.name(name() + ".total_refs")
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.desc("Total number of references to valid blocks.")
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;
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sampledRefs
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.name(name() + ".sampled_refs")
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.desc("Sample count of references to valid blocks.")
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;
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avgRefs
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.name(name() + ".avg_refs")
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.desc("Average number of references to valid blocks.")
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;
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avgRefs = totalRefs/sampledRefs;
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warmupCycle
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.name(name() + ".warmup_cycle")
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.desc("Cycle when the warmup percentage was hit.")
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;
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occupancies
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.init(cache->system->maxMasters())
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.name(name() + ".occ_blocks")
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.desc("Average occupied blocks per requestor")
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.flags(nozero | nonan)
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;
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for (int i = 0; i < cache->system->maxMasters(); i++) {
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occupancies.subname(i, cache->system->getMasterName(i));
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}
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avgOccs
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.name(name() + ".occ_percent")
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.desc("Average percentage of cache occupancy")
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.flags(nozero | total)
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;
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for (int i = 0; i < cache->system->maxMasters(); i++) {
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avgOccs.subname(i, cache->system->getMasterName(i));
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}
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avgOccs = occupancies / Stats::constant(numBlocks);
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occupanciesTaskId
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.init(ContextSwitchTaskId::NumTaskId)
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.name(name() + ".occ_task_id_blocks")
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.desc("Occupied blocks per task id")
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.flags(nozero | nonan)
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;
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ageTaskId
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.init(ContextSwitchTaskId::NumTaskId, 5)
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.name(name() + ".age_task_id_blocks")
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.desc("Occupied blocks per task id")
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.flags(nozero | nonan)
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;
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percentOccsTaskId
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.name(name() + ".occ_task_id_percent")
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.desc("Percentage of cache occupancy per task id")
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.flags(nozero)
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;
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percentOccsTaskId = occupanciesTaskId / Stats::constant(numBlocks);
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tagAccesses
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.name(name() + ".tag_accesses")
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.desc("Number of tag accesses")
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;
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dataAccesses
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.name(name() + ".data_accesses")
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.desc("Number of data accesses")
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;
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registerDumpCallback(new BaseTagsDumpCallback(this));
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registerExitCallback(new BaseTagsCallback(this));
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}
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