165 lines
4.6 KiB
C++
165 lines
4.6 KiB
C++
/*
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* Copyright (c) 2013-2014 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ron Dreslinski
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* Mitch Hayenga
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*/
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/**
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* @file
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* Hardware Prefetcher Definition.
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*/
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#include "mem/cache/prefetch/base.hh"
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#include <list>
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#include "base/intmath.hh"
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#include "mem/cache/base.hh"
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#include "sim/system.hh"
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BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
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: ClockedObject(p), cache(nullptr), blkSize(0), lBlkSize(0),
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system(p->sys), onMiss(p->on_miss), onRead(p->on_read),
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onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
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masterId(system->getMasterId(name())),
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pageBytes(system->getPageBytes())
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{
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}
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void
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BasePrefetcher::setCache(BaseCache *_cache)
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{
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assert(!cache);
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cache = _cache;
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blkSize = cache->getBlockSize();
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lBlkSize = floorLog2(blkSize);
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}
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void
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BasePrefetcher::regStats()
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{
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ClockedObject::regStats();
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pfIssued
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.name(name() + ".num_hwpf_issued")
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.desc("number of hwpf issued")
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;
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}
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bool
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BasePrefetcher::observeAccess(const PacketPtr &pkt) const
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{
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Addr addr = pkt->getAddr();
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bool fetch = pkt->req->isInstFetch();
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bool read = pkt->isRead();
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bool inv = pkt->isInvalidate();
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bool is_secure = pkt->isSecure();
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if (pkt->req->isUncacheable()) return false;
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if (fetch && !onInst) return false;
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if (!fetch && !onData) return false;
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if (!fetch && read && !onRead) return false;
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if (!fetch && !read && !onWrite) return false;
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if (!fetch && !read && inv) return false;
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if (pkt->cmd == MemCmd::CleanEvict) return false;
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if (onMiss) {
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return !inCache(addr, is_secure) &&
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!inMissQueue(addr, is_secure);
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}
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return true;
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}
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bool
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BasePrefetcher::inCache(Addr addr, bool is_secure) const
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{
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if (cache->inCache(addr, is_secure)) {
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return true;
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}
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return false;
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}
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bool
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BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
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{
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if (cache->inMissQueue(addr, is_secure)) {
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return true;
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}
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return false;
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}
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bool
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BasePrefetcher::samePage(Addr a, Addr b) const
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{
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return roundDown(a, pageBytes) == roundDown(b, pageBytes);
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}
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Addr
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BasePrefetcher::blockAddress(Addr a) const
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{
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return a & ~(blkSize-1);
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}
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Addr
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BasePrefetcher::blockIndex(Addr a) const
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{
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return a >> lBlkSize;
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}
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Addr
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BasePrefetcher::pageAddress(Addr a) const
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{
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return roundDown(a, pageBytes);
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}
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Addr
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BasePrefetcher::pageOffset(Addr a) const
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{
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return a & (pageBytes - 1);
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}
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Addr
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BasePrefetcher::pageIthBlockAddress(Addr page, uint32_t blockIndex) const
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{
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return page + (blockIndex << lBlkSize);
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}
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