e16967941b
Previously DPRINTFs printing information about a packet would use ad hoc formats. This patch changes all DPRINTFs to use the print function defined by the packet class, making the packet printing format more uniform and easier to change. Change-Id: Idd436a9758d4bf70c86a574d524648b2a2580970 Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
615 lines
19 KiB
C++
615 lines
19 KiB
C++
/*
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* Copyright (c) 2012-2013, 2015-2016 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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* Steve Reinhardt
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* Ron Dreslinski
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*/
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/**
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* @file
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* Declares a basic cache interface BaseCache.
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*/
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#ifndef __MEM_CACHE_BASE_HH__
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#define __MEM_CACHE_BASE_HH__
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#include <algorithm>
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#include <list>
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#include <string>
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#include <vector>
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#include "base/misc.hh"
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#include "base/statistics.hh"
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "debug/Cache.hh"
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#include "debug/CachePort.hh"
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#include "mem/cache/mshr_queue.hh"
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#include "mem/cache/write_queue.hh"
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#include "mem/mem_object.hh"
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#include "mem/packet.hh"
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#include "mem/qport.hh"
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#include "mem/request.hh"
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#include "params/BaseCache.hh"
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#include "sim/eventq.hh"
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#include "sim/full_system.hh"
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#include "sim/sim_exit.hh"
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#include "sim/system.hh"
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/**
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* A basic cache interface. Implements some common functions for speed.
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*/
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class BaseCache : public MemObject
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{
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protected:
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/**
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* Indexes to enumerate the MSHR queues.
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*/
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enum MSHRQueueIndex {
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MSHRQueue_MSHRs,
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MSHRQueue_WriteBuffer
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};
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public:
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/**
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* Reasons for caches to be blocked.
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*/
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enum BlockedCause {
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Blocked_NoMSHRs = MSHRQueue_MSHRs,
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Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
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Blocked_NoTargets,
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NUM_BLOCKED_CAUSES
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};
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protected:
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/**
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* A cache master port is used for the memory-side port of the
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* cache, and in addition to the basic timing port that only sends
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* response packets through a transmit list, it also offers the
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* ability to schedule and send request packets (requests &
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* writebacks). The send event is scheduled through schedSendEvent,
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* and the sendDeferredPacket of the timing port is modified to
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* consider both the transmit list and the requests from the MSHR.
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*/
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class CacheMasterPort : public QueuedMasterPort
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{
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public:
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/**
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* Schedule a send of a request packet (from the MSHR). Note
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* that we could already have a retry outstanding.
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*/
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void schedSendEvent(Tick time)
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{
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DPRINTF(CachePort, "Scheduling send event at %llu\n", time);
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reqQueue.schedSendEvent(time);
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}
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protected:
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CacheMasterPort(const std::string &_name, BaseCache *_cache,
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ReqPacketQueue &_reqQueue,
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SnoopRespPacketQueue &_snoopRespQueue) :
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QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue)
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{ }
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/**
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* Memory-side port always snoops.
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*
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* @return always true
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*/
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virtual bool isSnooping() const { return true; }
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};
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/**
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* A cache slave port is used for the CPU-side port of the cache,
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* and it is basically a simple timing port that uses a transmit
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* list for responses to the CPU (or connected master). In
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* addition, it has the functionality to block the port for
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* incoming requests. If blocked, the port will issue a retry once
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* unblocked.
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*/
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class CacheSlavePort : public QueuedSlavePort
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{
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public:
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/** Do not accept any new requests. */
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void setBlocked();
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/** Return to normal operation and accept new requests. */
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void clearBlocked();
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bool isBlocked() const { return blocked; }
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protected:
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CacheSlavePort(const std::string &_name, BaseCache *_cache,
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const std::string &_label);
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/** A normal packet queue used to store responses. */
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RespPacketQueue queue;
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bool blocked;
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bool mustSendRetry;
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private:
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void processSendRetry();
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EventWrapper<CacheSlavePort,
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&CacheSlavePort::processSendRetry> sendRetryEvent;
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};
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CacheSlavePort *cpuSidePort;
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CacheMasterPort *memSidePort;
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protected:
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/** Miss status registers */
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MSHRQueue mshrQueue;
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/** Write/writeback buffer */
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WriteQueue writeBuffer;
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/**
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* Mark a request as in service (sent downstream in the memory
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* system), effectively making this MSHR the ordering point.
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*/
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void markInService(MSHR *mshr, bool pending_modified_resp)
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{
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bool wasFull = mshrQueue.isFull();
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mshrQueue.markInService(mshr, pending_modified_resp);
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if (wasFull && !mshrQueue.isFull()) {
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clearBlocked(Blocked_NoMSHRs);
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}
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}
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void markInService(WriteQueueEntry *entry)
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{
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bool wasFull = writeBuffer.isFull();
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writeBuffer.markInService(entry);
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if (wasFull && !writeBuffer.isFull()) {
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clearBlocked(Blocked_NoWBBuffers);
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}
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}
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/**
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* Determine if we should allocate on a fill or not.
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*
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* @param cmd Packet command being added as an MSHR target
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*
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* @return Whether we should allocate on a fill or not
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*/
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virtual bool allocOnFill(MemCmd cmd) const = 0;
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/**
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* Write back dirty blocks in the cache using functional accesses.
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*/
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virtual void memWriteback() = 0;
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/**
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* Invalidates all blocks in the cache.
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*
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* @warn Dirty cache lines will not be written back to
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* memory. Make sure to call functionalWriteback() first if you
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* want the to write them to memory.
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*/
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virtual void memInvalidate() = 0;
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/**
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* Determine if there are any dirty blocks in the cache.
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*
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* \return true if at least one block is dirty, false otherwise.
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*/
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virtual bool isDirty() const = 0;
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/**
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* Determine if an address is in the ranges covered by this
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* cache. This is useful to filter snoops.
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*
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* @param addr Address to check against
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*
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* @return If the address in question is in range
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*/
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bool inRange(Addr addr) const;
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/** Block size of this cache */
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const unsigned blkSize;
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/**
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* The latency of tag lookup of a cache. It occurs when there is
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* an access to the cache.
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*/
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const Cycles lookupLatency;
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/**
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* The latency of data access of a cache. It occurs when there is
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* an access to the cache.
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*/
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const Cycles dataLatency;
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/**
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* This is the forward latency of the cache. It occurs when there
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* is a cache miss and a request is forwarded downstream, in
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* particular an outbound miss.
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*/
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const Cycles forwardLatency;
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/** The latency to fill a cache block */
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const Cycles fillLatency;
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/**
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* The latency of sending reponse to its upper level cache/core on
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* a linefill. The responseLatency parameter captures this
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* latency.
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*/
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const Cycles responseLatency;
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/** The number of targets for each MSHR. */
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const int numTarget;
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/** Do we forward snoops from mem side port through to cpu side port? */
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bool forwardSnoops;
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/**
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* Is this cache read only, for example the instruction cache, or
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* table-walker cache. A cache that is read only should never see
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* any writes, and should never get any dirty data (and hence
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* never have to do any writebacks).
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*/
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const bool isReadOnly;
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/**
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* Bit vector of the blocking reasons for the access path.
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* @sa #BlockedCause
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*/
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uint8_t blocked;
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/** Increasing order number assigned to each incoming request. */
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uint64_t order;
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/** Stores time the cache blocked for statistics. */
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Cycles blockedCycle;
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/** Pointer to the MSHR that has no targets. */
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MSHR *noTargetMSHR;
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/** The number of misses to trigger an exit event. */
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Counter missCount;
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/**
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* The address range to which the cache responds on the CPU side.
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* Normally this is all possible memory addresses. */
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const AddrRangeList addrRanges;
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public:
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/** System we are currently operating in. */
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System *system;
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// Statistics
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/**
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* @addtogroup CacheStatistics
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* @{
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*/
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/** Number of hits per thread for each type of command.
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@sa Packet::Command */
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Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
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/** Number of hits for demand accesses. */
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Stats::Formula demandHits;
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/** Number of hit for all accesses. */
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Stats::Formula overallHits;
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/** Number of misses per thread for each type of command.
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@sa Packet::Command */
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Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
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/** Number of misses for demand accesses. */
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Stats::Formula demandMisses;
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/** Number of misses for all accesses. */
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Stats::Formula overallMisses;
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/**
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* Total number of cycles per thread/command spent waiting for a miss.
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* Used to calculate the average miss latency.
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*/
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Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
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/** Total number of cycles spent waiting for demand misses. */
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Stats::Formula demandMissLatency;
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/** Total number of cycles spent waiting for all misses. */
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Stats::Formula overallMissLatency;
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/** The number of accesses per command and thread. */
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Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
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/** The number of demand accesses. */
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Stats::Formula demandAccesses;
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/** The number of overall accesses. */
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Stats::Formula overallAccesses;
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/** The miss rate per command and thread. */
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Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
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/** The miss rate of all demand accesses. */
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Stats::Formula demandMissRate;
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/** The miss rate for all accesses. */
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Stats::Formula overallMissRate;
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/** The average miss latency per command and thread. */
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Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
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/** The average miss latency for demand misses. */
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Stats::Formula demandAvgMissLatency;
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/** The average miss latency for all misses. */
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Stats::Formula overallAvgMissLatency;
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/** The total number of cycles blocked for each blocked cause. */
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Stats::Vector blocked_cycles;
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/** The number of times this cache blocked for each blocked cause. */
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Stats::Vector blocked_causes;
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/** The average number of cycles blocked for each blocked cause. */
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Stats::Formula avg_blocked;
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/** The number of times a HW-prefetched block is evicted w/o reference. */
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Stats::Scalar unusedPrefetches;
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/** Number of blocks written back per thread. */
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Stats::Vector writebacks;
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/** Number of misses that hit in the MSHRs per command and thread. */
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Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
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/** Demand misses that hit in the MSHRs. */
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Stats::Formula demandMshrHits;
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/** Total number of misses that hit in the MSHRs. */
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Stats::Formula overallMshrHits;
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/** Number of misses that miss in the MSHRs, per command and thread. */
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Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
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/** Demand misses that miss in the MSHRs. */
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Stats::Formula demandMshrMisses;
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/** Total number of misses that miss in the MSHRs. */
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Stats::Formula overallMshrMisses;
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/** Number of misses that miss in the MSHRs, per command and thread. */
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Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
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/** Total number of misses that miss in the MSHRs. */
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Stats::Formula overallMshrUncacheable;
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/** Total cycle latency of each MSHR miss, per command and thread. */
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Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
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/** Total cycle latency of demand MSHR misses. */
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Stats::Formula demandMshrMissLatency;
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/** Total cycle latency of overall MSHR misses. */
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Stats::Formula overallMshrMissLatency;
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/** Total cycle latency of each MSHR miss, per command and thread. */
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Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
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/** Total cycle latency of overall MSHR misses. */
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Stats::Formula overallMshrUncacheableLatency;
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#if 0
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/** The total number of MSHR accesses per command and thread. */
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Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
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/** The total number of demand MSHR accesses. */
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Stats::Formula demandMshrAccesses;
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/** The total number of MSHR accesses. */
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Stats::Formula overallMshrAccesses;
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#endif
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/** The miss rate in the MSHRs pre command and thread. */
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Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
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/** The demand miss rate in the MSHRs. */
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Stats::Formula demandMshrMissRate;
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/** The overall miss rate in the MSHRs. */
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Stats::Formula overallMshrMissRate;
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/** The average latency of an MSHR miss, per command and thread. */
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Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
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/** The average latency of a demand MSHR miss. */
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Stats::Formula demandAvgMshrMissLatency;
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/** The average overall latency of an MSHR miss. */
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Stats::Formula overallAvgMshrMissLatency;
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/** The average latency of an MSHR miss, per command and thread. */
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Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
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/** The average overall latency of an MSHR miss. */
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Stats::Formula overallAvgMshrUncacheableLatency;
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/**
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* @}
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*/
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/**
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* Register stats for this object.
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*/
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virtual void regStats();
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public:
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BaseCache(const BaseCacheParams *p, unsigned blk_size);
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~BaseCache() {}
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virtual void init();
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virtual BaseMasterPort &getMasterPort(const std::string &if_name,
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PortID idx = InvalidPortID);
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virtual BaseSlavePort &getSlavePort(const std::string &if_name,
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PortID idx = InvalidPortID);
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/**
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* Query block size of a cache.
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* @return The block size
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*/
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unsigned
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getBlockSize() const
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{
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return blkSize;
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}
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Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
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const AddrRangeList &getAddrRanges() const { return addrRanges; }
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MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
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{
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MSHR *mshr = mshrQueue.allocate(blockAlign(pkt->getAddr()), blkSize,
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pkt, time, order++,
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allocOnFill(pkt->cmd));
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if (mshrQueue.isFull()) {
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setBlocked((BlockedCause)MSHRQueue_MSHRs);
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}
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if (sched_send) {
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// schedule the send
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schedMemSideSendEvent(time);
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}
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return mshr;
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}
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void allocateWriteBuffer(PacketPtr pkt, Tick time)
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{
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// should only see writes or clean evicts here
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assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);
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Addr blk_addr = blockAlign(pkt->getAddr());
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WriteQueueEntry *wq_entry =
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writeBuffer.findMatch(blk_addr, pkt->isSecure());
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if (wq_entry && !wq_entry->inService) {
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DPRINTF(Cache, "Potential to merge writeback %s", pkt->print());
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}
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writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++);
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if (writeBuffer.isFull()) {
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setBlocked((BlockedCause)MSHRQueue_WriteBuffer);
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}
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// schedule the send
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schedMemSideSendEvent(time);
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}
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/**
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* Returns true if the cache is blocked for accesses.
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*/
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bool isBlocked() const
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{
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return blocked != 0;
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}
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|
|
|
/**
|
|
* Marks the access path of the cache as blocked for the given cause. This
|
|
* also sets the blocked flag in the slave interface.
|
|
* @param cause The reason for the cache blocking.
|
|
*/
|
|
void setBlocked(BlockedCause cause)
|
|
{
|
|
uint8_t flag = 1 << cause;
|
|
if (blocked == 0) {
|
|
blocked_causes[cause]++;
|
|
blockedCycle = curCycle();
|
|
cpuSidePort->setBlocked();
|
|
}
|
|
blocked |= flag;
|
|
DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
|
|
}
|
|
|
|
/**
|
|
* Marks the cache as unblocked for the given cause. This also clears the
|
|
* blocked flags in the appropriate interfaces.
|
|
* @param cause The newly unblocked cause.
|
|
* @warning Calling this function can cause a blocked request on the bus to
|
|
* access the cache. The cache must be in a state to handle that request.
|
|
*/
|
|
void clearBlocked(BlockedCause cause)
|
|
{
|
|
uint8_t flag = 1 << cause;
|
|
blocked &= ~flag;
|
|
DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
|
|
if (blocked == 0) {
|
|
blocked_cycles[cause] += curCycle() - blockedCycle;
|
|
cpuSidePort->clearBlocked();
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Schedule a send event for the memory-side port. If already
|
|
* scheduled, this may reschedule the event at an earlier
|
|
* time. When the specified time is reached, the port is free to
|
|
* send either a response, a request, or a prefetch request.
|
|
*
|
|
* @param time The time when to attempt sending a packet.
|
|
*/
|
|
void schedMemSideSendEvent(Tick time)
|
|
{
|
|
memSidePort->schedSendEvent(time);
|
|
}
|
|
|
|
virtual bool inCache(Addr addr, bool is_secure) const = 0;
|
|
|
|
virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
|
|
|
|
void incMissCount(PacketPtr pkt)
|
|
{
|
|
assert(pkt->req->masterId() < system->maxMasters());
|
|
misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
|
|
pkt->req->incAccessDepth();
|
|
if (missCount) {
|
|
--missCount;
|
|
if (missCount == 0)
|
|
exitSimLoop("A cache reached the maximum miss count");
|
|
}
|
|
}
|
|
void incHitCount(PacketPtr pkt)
|
|
{
|
|
assert(pkt->req->masterId() < system->maxMasters());
|
|
hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
|
|
|
|
}
|
|
|
|
};
|
|
|
|
#endif //__MEM_CACHE_BASE_HH__
|