1470dae8e9
--HG-- rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc rename : src/arch/sparc/system.cc => src/arch/arm/system.cc rename : src/arch/sparc/system.hh => src/arch/arm/system.hh rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh
108 lines
3.3 KiB
C++
108 lines
3.3 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* Copyright (c) 2009 ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/**
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* @file
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* Declaration of top level class for the Versatile platform chips. This class just
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* retains pointers to all its children so the children can communicate.
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*/
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#ifndef __DEV_ARM_VERSATILE_HH__
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#define __DEV_ARM_VERSATILE_HH__
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#include "dev/platform.hh"
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#include "params/Versatile.hh"
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class IdeController;
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class System;
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class Versatile : public Platform
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{
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public:
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/** Pointer to the system */
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System *system;
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public:
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typedef VersatileParams Params;
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/**
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* Constructor for the Tsunami Class.
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* @param name name of the object
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* @param s system the object belongs to
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* @param intctrl pointer to the interrupt controller
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*/
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Versatile(const Params *p);
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/**
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* Return the interrupting frequency to AlphaAccess
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* @return frequency of RTC interrupts
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*/
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virtual Tick intrFrequency();
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/**
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* Cause the cpu to post a serial interrupt to the CPU.
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*/
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virtual void postConsoleInt();
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/**
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* Clear a posted CPU interrupt
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*/
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virtual void clearConsoleInt();
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/**
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* Cause the chipset to post a cpi interrupt to the CPU.
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*/
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virtual void postPciInt(int line);
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/**
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* Clear a posted PCI->CPU interrupt
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*/
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virtual void clearPciInt(int line);
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virtual Addr pciToDma(Addr pciAddr) const;
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/**
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* Calculate the configuration address given a bus/dev/func.
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*/
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virtual Addr calcPciConfigAddr(int bus, int dev, int func);
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/**
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* Calculate the address for an IO location on the PCI bus.
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*/
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virtual Addr calcPciIOAddr(Addr addr);
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/**
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* Calculate the address for a memory location on the PCI bus.
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*/
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virtual Addr calcPciMemAddr(Addr addr);
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};
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#endif // __DEV_ARM_VERSATILE_HH__
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