1470dae8e9
--HG-- rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc rename : src/arch/sparc/system.cc => src/arch/arm/system.cc rename : src/arch/sparc/system.hh => src/arch/arm/system.hh rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh
122 lines
2.9 KiB
C++
122 lines
2.9 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* Copyright (c) 2009 ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#ifndef __ARCH_ARM_INTERRUPT_HH__
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#define __ARCH_ARM_INTERRUPT_HH__
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#include "arch/arm/faults.hh"
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#include "arch/arm/isa_traits.hh"
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#include "arch/arm/registers.hh"
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#include "cpu/thread_context.hh"
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#include "params/ArmInterrupts.hh"
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#include "sim/sim_object.hh"
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namespace ArmISA
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{
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class Interrupts : public SimObject
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{
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private:
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BaseCPU * cpu;
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uint64_t intStatus;
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public:
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void
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setCPU(BaseCPU * _cpu)
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{
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cpu = _cpu;
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}
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typedef ArmInterruptsParams Params;
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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Interrupts(Params * p) : SimObject(p), cpu(NULL)
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{
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clearAll();
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}
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void
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post(int int_num, int index)
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{
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}
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void
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clear(int int_num, int index)
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{
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}
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void
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clearAll()
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{
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intStatus = 0;
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}
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bool
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checkInterrupts(ThreadContext *tc) const
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{
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return intStatus;
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}
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Fault
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getInterrupt(ThreadContext *tc)
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{
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warn_once("ARM Interrupts not handled\n");
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return NoFault;
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}
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void
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updateIntrInfo(ThreadContext *tc)
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{
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}
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void
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serialize(std::ostream &os)
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{
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}
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void
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unserialize(Checkpoint *cp, const std::string §ion)
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{
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}
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};
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} // namespace ARM_ISA
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#endif // __ARCH_ARM_INTERRUPT_HH__
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