Ali Saidi 147095cb08 Mem: Fix issue with prefetches originating at non-L1 caches getting stale data ... Prefetch requests issued from the L2 or below wouldn't check if valid data is present higher in the system. If a prefetch into the L2 occured at the same time as writeback from a higher-level cache the dirty data could be replaced in by unmodified data in memory.		2011-07-15 11:53:35 -05:00
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arch	ARM: Fix SWP/SWPB undefined instruction behavior	2011-07-15 11:53:34 -05:00
base	Loader: Handle bad section names when loading an ELF file.	2011-06-12 23:52:21 -07:00
cpu	O3: Create a pipeline activity viewer for the O3 CPU model.	2011-07-15 11:53:35 -05:00
dev	IO: Handle case where ISA Fake device is being used as a fake memory.	2011-07-10 12:56:08 -05:00
doxygen
kern	scons: rename TraceFlags to DebugFlags	2011-06-02 17:36:21 -07:00
mem	Mem: Fix issue with prefetches originating at non-L1 caches getting stale data	2011-07-15 11:53:35 -05:00
python	O3: Make sure fetch doesn't go off into the weeds during speculation.	2011-07-10 12:56:08 -05:00
sim	O3: Make sure fetch doesn't go off into the weeds during speculation.	2011-07-10 12:56:08 -05:00
unittest	copyright: clean up copyright blocks	2011-06-02 14:36:35 -07:00
Doxyfile
SConscript	scons: rename TraceFlags to DebugFlags	2011-06-02 17:36:21 -07:00