199 lines
7.6 KiB
Python
199 lines
7.6 KiB
Python
# Copyright (c) 2014-2015 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Hansson
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import optparse
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import m5
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from m5.objects import *
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from m5.util import addToPath
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from m5.internal.stats import periodicStatDump
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addToPath('../common')
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import MemConfig
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# this script is helpful to sweep the efficiency of a specific memory
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# controller configuration, by varying the number of banks accessed,
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# and the sequential stride size (how many bytes per activate), and
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# observe what bus utilisation (bandwidth) is achieved
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parser = optparse.OptionParser()
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# Use a single-channel DDR3-1600 x64 by default
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parser.add_option("--mem-type", type="choice", default="ddr3_1600_x64",
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choices=MemConfig.mem_names(),
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help = "type of memory to use")
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parser.add_option("--mem-ranks", "-r", type="int", default=1,
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help = "Number of ranks to iterate across")
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parser.add_option("--rd_perc", type="int", default=100,
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help = "Percentage of read commands")
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parser.add_option("--mode", type="choice", default="DRAM",
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choices=["DRAM", "DRAM_ROTATE"],
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help = "DRAM: Random traffic; \
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DRAM_ROTATE: Traffic rotating across banks and ranks")
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parser.add_option("--addr_map", type="int", default=1,
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help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo")
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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# at the moment we stay with the default open-adaptive page policy,
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# and address mapping
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# start with the system itself, using a multi-layer 1.5 GHz
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# crossbar, delivering 64 bytes / 5 cycles (one header cycle)
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# which amounts to 19.2 GByte/s per layer and thus per port
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system = System(membus = IOXBar(width = 16))
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system.clk_domain = SrcClockDomain(clock = '1.5GHz',
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voltage_domain =
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VoltageDomain(voltage = '1V'))
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# we are fine with 256 MB memory for now
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mem_range = AddrRange('256MB')
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system.mem_ranges = [mem_range]
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# force a single channel to match the assumptions in the DRAM traffic
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# generator
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options.mem_channels = 1
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MemConfig.config_mem(options, system)
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# the following assumes that we are using the native DRAM
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# controller, check to be sure
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if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
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fatal("This script assumes the memory is a DRAMCtrl subclass")
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# Set the address mapping based on input argument
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# Default to RoRaBaCoCh
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if options.addr_map == 0:
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system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh"
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elif options.addr_map == 1:
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system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh"
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else:
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fatal("Did not specify a valid address map argument")
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# stay in each state for 0.25 ms, long enough to warm things up, and
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# short enough to avoid hitting a refresh
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period = 250000000
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# this is where we go off piste, and print the traffic generator
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# configuration that we will later use, crazy but it works
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cfg_file_name = "configs/dram/sweep.cfg"
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cfg_file = open(cfg_file_name, 'w')
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# stay in each state as long as the dump/reset period, use the entire
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# range, issue transactions of the right DRAM burst size, and match
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# the DRAM maximum bandwidth to ensure that it is saturated
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# get the number of banks
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nbr_banks = system.mem_ctrls[0].banks_per_rank.value
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# determine the burst length in bytes
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burst_size = int((system.mem_ctrls[0].devices_per_rank.value *
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system.mem_ctrls[0].device_bus_width.value *
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system.mem_ctrls[0].burst_length.value) / 8)
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# next, get the page size in bytes
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page_size = system.mem_ctrls[0].devices_per_rank.value * \
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system.mem_ctrls[0].device_rowbuffer_size.value
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# match the maximum bandwidth of the memory, the parameter is in ns
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# and we need it in ticks
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itt = system.mem_ctrls[0].tBURST.value * 1000000000000
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# assume we start at 0
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max_addr = mem_range.end
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# use min of the page size and 512 bytes as that should be more than
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# enough
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max_stride = min(512, page_size)
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# now we create the state by iterating over the stride size from burst
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# size to the max stride, and from using only a single bank up to the
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# number of banks available
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nxt_state = 0
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for bank in range(1, nbr_banks + 1):
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for stride_size in range(burst_size, max_stride + 1, burst_size):
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cfg_file.write("STATE %d %d %s %d 0 %d %d "
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"%d %d %d %d %d %d %d %d %d\n" %
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(nxt_state, period, options.mode, options.rd_perc,
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max_addr, burst_size, itt, itt, 0, stride_size,
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page_size, nbr_banks, bank, options.addr_map,
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options.mem_ranks))
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nxt_state = nxt_state + 1
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cfg_file.write("INIT 0\n")
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# go through the states one by one
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for state in range(1, nxt_state):
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cfg_file.write("TRANSITION %d %d 1\n" % (state - 1, state))
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cfg_file.write("TRANSITION %d %d 1\n" % (nxt_state - 1, nxt_state - 1))
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cfg_file.close()
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# create a traffic generator, and point it to the file we just created
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system.tgen = TrafficGen(config_file = cfg_file_name)
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# add a communication monitor
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system.monitor = CommMonitor()
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# connect the traffic generator to the bus via a communication monitor
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system.tgen.port = system.monitor.slave
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system.monitor.master = system.membus.slave
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# connect the system port even if it is not used in this example
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system.system_port = system.membus.slave
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# every period, dump and reset all stats
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periodicStatDump(period)
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# run Forrest, run!
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root = Root(full_system = False, system = system)
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root.system.mem_mode = 'timing'
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m5.instantiate()
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m5.simulate(nxt_state * period)
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print "DRAM sweep with burst: %d, banks: %d, max stride: %d" % \
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(burst_size, nbr_banks, max_stride)
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