13f8dc981f
ticks for the most commonly accessed devices.
dev/baddev.cc:
Get rid of the constant cache access latency.
For unimportant devices, don't add any latency.
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart.cc:
dev/uart.hh:
make the cache access latency a parameter that is based on bus
ticks.
dev/io_device.cc:
dev/io_device.hh:
add an io latency variable
dev/ns_gige.hh:
this moved to io_device.hh
--HG--
extra : convert_revision : 4883130feeaef48abee492eddf0b8eb40eb94789
110 lines
3.2 KiB
C++
110 lines
3.2 KiB
C++
/*
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* Copyright (c) 2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* Defines a 8250 UART
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*/
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#ifndef __TSUNAMI_UART_HH__
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#define __TSUNAMI_UART_HH__
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#include "dev/tsunamireg.h"
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#include "base/range.hh"
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#include "dev/io_device.hh"
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class SimConsole;
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class Platform;
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const int RX_INT = 0x1;
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const int TX_INT = 0x2;
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class Uart : public PioDevice
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{
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private:
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Addr addr;
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Addr size;
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SimConsole *cons;
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protected:
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int readAddr; // tlaser only
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uint8_t IER, DLAB, LCR, MCR;
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int status;
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class IntrEvent : public Event
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{
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protected:
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Uart *uart;
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int intrBit;
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public:
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IntrEvent(Uart *u, int bit);
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virtual void process();
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virtual const char *description();
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void scheduleIntr();
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};
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IntrEvent txIntrEvent;
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IntrEvent rxIntrEvent;
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Platform *platform;
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public:
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Uart(const string &name, SimConsole *c, MemoryController *mmu,
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Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
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Platform *p);
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Fault read(MemReqPtr &req, uint8_t *data);
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Fault write(MemReqPtr &req, const uint8_t *data);
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/**
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* Inform the uart that there is data available.
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*/
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void dataAvailable();
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/**
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* Return if we have an interrupt pending
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* @return interrupt status
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*/
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bool intStatus() { return status ? true : false; }
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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/**
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* Return how long this access will take.
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* @param req the memory request to calcuate
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* @return Tick when the request is done
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*/
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Tick cacheAccess(MemReqPtr &req);
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};
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#endif // __TSUNAMI_UART_HH__
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