13c005a8af
--HG-- rename : cpu/base_cpu.cc => cpu/base.cc rename : cpu/base_cpu.hh => cpu/base.hh rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh rename : cpu/full_cpu/smt.hh => cpu/smt.hh rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032
181 lines
6.4 KiB
C++
181 lines
6.4 KiB
C++
/*
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* Copyright (c) 2003-2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "base/loader/symtab.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/exec_context.hh"
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#include "kern/tru64/tru64_events.hh"
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#include "kern/tru64/tru64_system.hh"
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#include "kern/system_events.hh"
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#include "mem/functional/memory_control.hh"
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#include "mem/functional/physical.hh"
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#include "sim/builder.hh"
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#include "targetarch/isa_traits.hh"
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#include "targetarch/vtophys.hh"
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using namespace std;
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Tru64System::Tru64System(Tru64System::Params *p)
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: System(p)
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{
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Addr addr = 0;
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if (kernelSymtab->findAddress("enable_async_printf", addr)) {
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Addr paddr = vtophys(physmem, addr);
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uint8_t *enable_async_printf =
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physmem->dma_addr(paddr, sizeof(uint32_t));
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if (enable_async_printf)
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*(uint32_t *)enable_async_printf = 0;
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}
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#ifdef DEBUG
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kernelPanicEvent = new BreakPCEvent(&pcEventQueue, "kernel panic");
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if (kernelSymtab->findAddress("panic", addr))
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kernelPanicEvent->schedule(addr);
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else
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panic("could not find kernel symbol \'panic\'");
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#endif
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badaddrEvent = new BadAddrEvent(&pcEventQueue, "badaddr");
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if (kernelSymtab->findAddress("badaddr", addr))
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badaddrEvent->schedule(addr);
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else
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panic("could not find kernel symbol \'badaddr\'");
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skipPowerStateEvent = new SkipFuncEvent(&pcEventQueue,
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"tl_v48_capture_power_state");
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if (kernelSymtab->findAddress("tl_v48_capture_power_state", addr))
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skipPowerStateEvent->schedule(addr);
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skipScavengeBootEvent = new SkipFuncEvent(&pcEventQueue,
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"pmap_scavenge_boot");
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if (kernelSymtab->findAddress("pmap_scavenge_boot", addr))
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skipScavengeBootEvent->schedule(addr);
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#if TRACING_ON
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printfEvent = new PrintfEvent(&pcEventQueue, "printf");
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if (kernelSymtab->findAddress("printf", addr))
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printfEvent->schedule(addr);
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debugPrintfEvent = new DebugPrintfEvent(&pcEventQueue, "debug_printf",
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false);
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if (kernelSymtab->findAddress("m5printf", addr))
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debugPrintfEvent->schedule(addr);
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debugPrintfrEvent = new DebugPrintfEvent(&pcEventQueue, "debug_printfr",
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true);
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if (kernelSymtab->findAddress("m5printfr", addr))
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debugPrintfrEvent->schedule(addr);
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dumpMbufEvent = new DumpMbufEvent(&pcEventQueue, "dump_mbuf");
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if (kernelSymtab->findAddress("m5_dump_mbuf", addr))
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dumpMbufEvent->schedule(addr);
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#endif
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}
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Tru64System::~Tru64System()
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{
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#ifdef DEBUG
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delete kernelPanicEvent;
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#endif
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delete badaddrEvent;
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delete skipPowerStateEvent;
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delete skipScavengeBootEvent;
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#if TRACING_ON
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delete printfEvent;
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delete debugPrintfEvent;
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delete debugPrintfrEvent;
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delete dumpMbufEvent;
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#endif
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tru64System)
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Param<Tick> boot_cpu_frequency;
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SimObjectParam<MemoryController *> memctrl;
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SimObjectParam<PhysicalMemory *> physmem;
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Param<string> kernel;
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Param<string> console;
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Param<string> pal;
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Param<string> boot_osflags;
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Param<string> readfile;
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Param<unsigned int> init_param;
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Param<uint64_t> system_type;
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Param<uint64_t> system_rev;
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Param<bool> bin;
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VectorParam<string> binned_fns;
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END_DECLARE_SIM_OBJECT_PARAMS(Tru64System)
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BEGIN_INIT_SIM_OBJECT_PARAMS(Tru64System)
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INIT_PARAM(boot_cpu_frequency, "frequency of the boot cpu"),
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INIT_PARAM(memctrl, "memory controller"),
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INIT_PARAM(physmem, "phsyical memory"),
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INIT_PARAM(kernel, "file that contains the kernel code"),
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INIT_PARAM(console, "file that contains the console code"),
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INIT_PARAM(pal, "file that contains palcode"),
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INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
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"a"),
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INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
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INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
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INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 12),
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INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 2<<1),
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INIT_PARAM_DFLT(bin, "is this system to be binned", false),
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INIT_PARAM(binned_fns, "functions to be broken down and binned")
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END_INIT_SIM_OBJECT_PARAMS(Tru64System)
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CREATE_SIM_OBJECT(Tru64System)
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{
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System::Params *p = new System::Params;
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p->name = getInstanceName();
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p->boot_cpu_frequency = boot_cpu_frequency;
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p->memctrl = memctrl;
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p->physmem = physmem;
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p->kernel_path = kernel;
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p->console_path = console;
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p->palcode = pal;
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p->boot_osflags = boot_osflags;
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p->init_param = init_param;
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p->readfile = readfile;
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p->system_type = system_type;
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p->system_rev = system_rev;
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p->bin = bin;
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p->binned_fns = binned_fns;
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p->bin_int = false;
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return new Tru64System(p);
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}
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REGISTER_SIM_OBJECT("Tru64System", Tru64System)
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