330 lines
37 KiB
Text
330 lines
37 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000017 # Number of seconds simulated
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sim_ticks 16769000 # Number of ticks simulated
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final_tick 16769000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 142484 # Simulator instruction rate (inst/s)
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host_op_rate 142326 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 925222654 # Simulator tick rate (ticks/s)
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host_mem_usage 208204 # Number of bytes of host memory used
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host_seconds 0.02 # Real time elapsed on the host
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sim_insts 2577 # Number of instructions simulated
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sim_ops 2577 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read 15680 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 10432 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 0 # Number of bytes written to this memory
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system.physmem.num_reads 245 # Number of read requests responded to by this memory
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system.physmem.num_writes 0 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 935058739 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 622100304 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total 935058739 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 415 # DTB read hits
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system.cpu.dtb.read_misses 4 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 419 # DTB read accesses
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system.cpu.dtb.write_hits 294 # DTB write hits
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system.cpu.dtb.write_misses 4 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 298 # DTB write accesses
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system.cpu.dtb.data_hits 709 # DTB hits
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system.cpu.dtb.data_misses 8 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 717 # DTB accesses
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system.cpu.itb.fetch_hits 2586 # ITB hits
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system.cpu.itb.fetch_misses 11 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 2597 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 4 # Number of system calls
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system.cpu.numCycles 33538 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 2577 # Number of instructions committed
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system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
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system.cpu.num_func_calls 140 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
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system.cpu.num_int_insts 2375 # number of integer instructions
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system.cpu.num_fp_insts 6 # number of float instructions
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system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
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system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 717 # number of memory refs
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system.cpu.num_load_insts 419 # Number of load instructions
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system.cpu.num_store_insts 298 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 33538 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.tagsinuse 80.003762 # Cycle average of tags in use
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system.cpu.icache.total_refs 2423 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 80.003762 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.039064 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.039064 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 2423 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 2423 # number of overall hits
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system.cpu.icache.overall_hits::total 2423 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 163 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses
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system.cpu.icache.overall_misses::total 163 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 9128000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 9128000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 9128000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 9128000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 9128000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 9128000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 2586 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 2586 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 2586 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.063032 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8639000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 8639000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8639000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 8639000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8639000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 8639000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use
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system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 47.418751 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.011577 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.011577 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits
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system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits
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system.cpu.dcache.overall_hits::total 627 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses
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system.cpu.dcache.overall_misses::total 82 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 1512000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 1512000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 4592000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 4592000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 4592000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 4592000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4346000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 4346000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4346000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 4346000 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses
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system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::cpu.inst 80.120406 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 26.980800 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::cpu.inst 0.002445 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.000823 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::total 0.003268 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses
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system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses
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system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::cpu.data 82 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::total 245 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses
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system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses
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system.cpu.l2cache.overall_misses::total 245 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8476000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::total 11336000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1404000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::total 1404000 # number of ReadExReq miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.inst 8476000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.data 4264000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::total 12740000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 8476000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 4264000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::total 12740000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 163 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 218 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 163 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 82 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 245 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 163 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 82 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 245 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 218 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 245 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6520000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8720000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1080000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1080000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6520000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3280000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 9800000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6520000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3280000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 9800000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|