gem5/ext/sst/libgem5.cc
Curtis Dunham f05cb84ed1 ext: Add SST connector
This patch adds a connector that allows gem5 to be used as a component
in SST (Structural Simulation Toolkit, sst-simulator.org). At a high
level, this allows memory traffic to pass between the two simulators.
SST Links are roughly analogous to gem5 Ports, although Links do not
have a notion of master and slave. This distinction is important to
gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave
must be used, and similarly when connecting the memory side of SST cache
to a gem5 port (for memory <-> I/O), an ExternalMaster must be used.

These connectors handle the administrative aspects of gem5
(initialization, simulation, shutdown) as well as translating SST's
MemEvents into gem5 Packets and vice-versa.
2015-04-08 15:56:06 -05:00

84 lines
3.3 KiB
C++

// Copyright (c) 2015 ARM Limited
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#include <sst_config.h>
#include <sst/core/serialization.h>
#include <sst/core/element.h>
#include <sst/core/component.h>
#include "gem5.hh"
static
SST::Component* create_gem5(SST::ComponentId_t id, SST::Params &params)
{
return new SST::gem5::gem5Component(id, params);
}
static const SST::ElementInfoParam gem5_params[] = {
{"cmd", "gem5 command to execute."},
{"comp_debug", "Debug information from the component: 0 (off), 1 (stdout),"
" 2 (stderr), 3(file)"},
{"frequency", "Frequency with which to call into gem5"},
{NULL, NULL}
};
static const SST::ElementInfoComponent components[] = {
{ "gem5",
"gem5 simulation component",
NULL,
create_gem5,
gem5_params
},
{ NULL, NULL, NULL, NULL, NULL }
};
extern "C" {
SST::ElementLibraryInfo gem5_eli = {
"gem5",
"gem5 Simulation",
components,
};
}