c274057840
Add revision 9adf9d6e2d889a483a92136c96eb8a434d360561 of NoMali-model from https://github.com/ARM-software/nomali-model. This library implements the register interface of the Mali T6xx/T7xx series GPUs, but doesn't do any rendering. It can be used to hide the effects of software rendering.
177 lines
4 KiB
C++
177 lines
4 KiB
C++
/*
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* Copyright (c) 2014-2015 ARM Limited
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* All rights reserved
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* Authors: Andreas Sandberg
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*/
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#include "gpucontrol.hh"
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#include "gpu.hh"
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#include "regutils.hh"
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namespace NoMali {
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typedef void (GPUControl::*GpuCmdHandler)(uint32_t);
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const std::vector<GpuCmdHandler> GPUControl::cmds {
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&GPUControl::cmdNop, // GPU_COMMAND_NOP
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&GPUControl::cmdSoftReset, // GPU_COMMAND_SOFT_RESET
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&GPUControl::cmdHardReset, // GPU_COMMAND_HARD_RESET
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&GPUControl::cmdPerfCntClear, // GPU_COMMAND_PRFCNT_CLEAR
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&GPUControl::cmdPerfCntSample, // GPU_COMMAND_PRFCNT_SAMPLE
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&GPUControl::cmdCycleCountStart, // GPU_COMMAND_CYCLE_COUNT_START
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&GPUControl::cmdCycleCountStop, // GPU_COMMAND_COUNT_STOP
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&GPUControl::cmdCleanCaches, // GPU_COMMAND_CLEAN_CACHES
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&GPUControl::cmdCleanInvCaches, // GPU_COMMAND_CLEAN_INV_CACHES
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};
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GPUControl::GPUControl(GPU &_gpu)
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: GPUBlockInt(_gpu,
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RegAddr(GPU_IRQ_RAWSTAT),
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RegAddr(GPU_IRQ_CLEAR),
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RegAddr(GPU_IRQ_MASK),
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RegAddr(GPU_IRQ_STATUS))
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{
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}
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GPUControl::~GPUControl()
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{
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}
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void
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GPUControl::reset()
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{
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GPUBlock::reset();
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}
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void
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GPUControl::writeReg(RegAddr addr, uint32_t value)
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{
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switch (addr.value) {
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case GPU_IRQ_RAWSTAT:
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case GPU_IRQ_CLEAR:
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case GPU_IRQ_MASK:
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case GPU_IRQ_STATUS:
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GPUBlockInt::writeReg(addr, value);
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break;
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case GPU_COMMAND:
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gpuCommand(value);
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break;
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case SHADER_PWRON_LO:
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case SHADER_PWRON_HI:
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case TILER_PWRON_LO:
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case TILER_PWRON_HI:
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case L2_PWRON_LO:
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case L2_PWRON_HI:
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case L3_PWRON_LO:
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case L3_PWRON_HI: {
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const RegAddr ready_reg(SHADER_READY_LO +
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(addr.value - SHADER_PWRON_LO));
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const RegAddr present_reg(SHADER_PRESENT_LO +
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(addr.value - SHADER_PWRON_LO));
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regs[ready_reg] |= value & regs[present_reg];
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raiseInterrupt(POWER_CHANGED_SINGLE | POWER_CHANGED_ALL);
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} break;
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case SHADER_PWROFF_LO:
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case SHADER_PWROFF_HI:
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case TILER_PWROFF_LO:
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case TILER_PWROFF_HI:
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case L2_PWROFF_LO:
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case L2_PWROFF_HI:
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case L3_PWROFF_LO:
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case L3_PWROFF_HI: {
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const RegAddr ready_reg(SHADER_READY_LO +
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(addr.value - SHADER_PWROFF_LO));
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regs[ready_reg] &= ~value;
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raiseInterrupt(POWER_CHANGED_SINGLE | POWER_CHANGED_ALL);
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} break;
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default:
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// Ignore writes by default
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break;
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};
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}
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void
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GPUControl::onInterrupt(int set)
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{
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gpu.intGPU(set);
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}
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void
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GPUControl::gpuCommand(uint32_t cmd)
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{
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if (cmd < cmds.size())
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(this->*cmds[cmd])(cmd);
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}
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void
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GPUControl::cmdNop(uint32_t cmd)
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{
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}
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void
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GPUControl::cmdHardReset(uint32_t cmd)
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{
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gpu.reset();
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raiseInterrupt(RESET_COMPLETED);
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}
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void
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GPUControl::cmdSoftReset(uint32_t cmd)
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{
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gpu.reset();
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raiseInterrupt(RESET_COMPLETED);
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}
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void
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GPUControl::cmdPerfCntClear(uint32_t cmd)
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{
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}
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void
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GPUControl::cmdPerfCntSample(uint32_t cmd)
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{
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raiseInterrupt(PRFCNT_SAMPLE_COMPLETED);
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}
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void
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GPUControl::cmdCycleCountStart(uint32_t cmd)
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{
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}
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void
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GPUControl::cmdCycleCountStop(uint32_t cmd)
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{
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}
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void
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GPUControl::cmdCleanCaches(uint32_t cmd)
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{
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raiseInterrupt(CLEAN_CACHES_COMPLETED);
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}
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void
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GPUControl::cmdCleanInvCaches(uint32_t cmd)
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{
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raiseInterrupt(CLEAN_CACHES_COMPLETED);
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}
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}
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