arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/fake_syscall.cc: arch/alpha/faults.cc: arch/alpha/isa_desc: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/circlebuf.cc: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/cprintf.cc: base/cprintf.hh: base/fast_alloc.cc: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/exec_aout.h: base/loader/exec_ecoff.h: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/misc.cc: base/misc.hh: base/pollevent.cc: base/pollevent.hh: base/random.cc: base/random.hh: base/range.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/statistics.cc: base/statistics.hh: base/str.cc: base/trace.cc: base/trace.hh: cpu/base_cpu.cc: cpu/base_cpu.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: cpu/pc_event.cc: cpu/pc_event.hh: cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: cpu/static_inst.cc: cpu/static_inst.hh: dev/alpha_console.cc: dev/alpha_console.hh: dev/console.cc: dev/console.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/simple_disk.cc: dev/simple_disk.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: sim/debug.cc: sim/eventq.cc: sim/eventq.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/prog.cc: sim/prog.hh: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_object.cc: sim/sim_object.hh: sim/sim_time.cc: sim/system.cc: sim/system.hh: sim/universe.cc: test/circletest.cc: test/cprintftest.cc: test/initest.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/tap/tap.cc: Make include paths explicit. --HG-- extra : convert_revision : 941cbdc591fd4d3d1d9f095cd58fc23dd2d73840
433 lines
14 KiB
C++
433 lines
14 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __STATIC_INST_HH__
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#define __STATIC_INST_HH__
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#include <bitset>
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#include <string>
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#include "sim/host.hh"
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#include "base/hashmap.hh"
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#include "base/refcnt.hh"
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#include "cpu/full_cpu/op_class.hh"
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#include "targetarch/isa_traits.hh"
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// forward declarations
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class ExecContext;
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class SpecExecContext;
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class SimpleCPU;
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class CPU;
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class DynInst;
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class SymbolTable;
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namespace Trace {
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class InstRecord;
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}
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/**
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* Base, ISA-independent static instruction class.
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*
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* The main component of this class is the vector of flags and the
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* associated methods for reading them. Any object that can rely
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* solely on these flags can process instructions without being
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* recompiled for multiple ISAs.
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*/
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class StaticInstBase : public RefCounted
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{
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protected:
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/// Set of boolean static instruction properties.
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///
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/// Notes:
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/// - The IsInteger and IsFloating flags are based on the class of
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/// registers accessed by the instruction. Although most
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/// instructions will have exactly one of these two flags set, it
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/// is possible for an instruction to have neither (e.g., direct
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/// unconditional branches, memory barriers) or both (e.g., an
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/// FP/int conversion).
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/// - If IsMemRef is set, then exactly one of IsLoad or IsStore
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/// will be set. Prefetches are marked as IsLoad, even if they
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/// prefetch exclusive copies.
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/// - If IsControl is set, then exactly one of IsDirectControl or
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/// IsIndirect Control will be set, and exactly one of
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/// IsCondControl or IsUncondControl will be set.
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///
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enum Flags {
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IsNop, ///< Is a no-op (no effect at all).
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IsInteger, ///< References integer regs.
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IsFloating, ///< References FP regs.
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IsMemRef, ///< References memory (load, store, or prefetch).
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IsLoad, ///< Reads from memory (load or prefetch).
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IsStore, ///< Writes to memory.
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IsInstPrefetch, ///< Instruction-cache prefetch.
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IsDataPrefetch, ///< Data-cache prefetch.
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IsControl, ///< Control transfer instruction.
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IsDirectControl, ///< PC relative control transfer.
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IsIndirectControl, ///< Register indirect control transfer.
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IsCondControl, ///< Conditional control transfer.
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IsUncondControl, ///< Unconditional control transfer.
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IsCall, ///< Subroutine call.
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IsReturn, ///< Subroutine return.
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IsThreadSync, ///< Thread synchronization operation.
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NumFlags
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};
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/// Flag values for this instruction.
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std::bitset<NumFlags> flags;
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/// See opClass().
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OpClass _opClass;
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/// See numSrcRegs().
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int8_t _numSrcRegs;
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/// See numDestRegs().
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int8_t _numDestRegs;
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/// The following are used to track physical register usage
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/// for machines with separate int & FP reg files.
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//@{
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int8_t _numFPDestRegs;
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int8_t _numIntDestRegs;
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//@}
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/// Constructor.
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/// It's important to initialize everything here to a sane
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/// default, since the decoder generally only overrides
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/// the fields that are meaningful for the particular
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/// instruction.
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StaticInstBase(OpClass __opClass)
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: _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
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_numFPDestRegs(0), _numIntDestRegs(0)
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{
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}
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public:
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/// @name Register information.
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/// The sum of numFPDestRegs() and numIntDestRegs() equals
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/// numDestRegs(). The former two functions are used to track
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/// physical register usage for machines with separate int & FP
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/// reg files.
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//@{
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/// Number of source registers.
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int8_t numSrcRegs() const { return _numSrcRegs; }
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/// Number of destination registers.
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int8_t numDestRegs() const { return _numDestRegs; }
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/// Number of floating-point destination regs.
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int8_t numFPDestRegs() const { return _numFPDestRegs; }
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/// Number of integer destination regs.
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int8_t numIntDestRegs() const { return _numIntDestRegs; }
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//@}
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/// @name Flag accessors.
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/// These functions are used to access the values of the various
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/// instruction property flags. See StaticInstBase::Flags for descriptions
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/// of the individual flags.
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//@{
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bool isNop() const { return flags[IsNop]; }
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bool isMemRef() const { return flags[IsMemRef]; }
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bool isLoad() const { return flags[IsLoad]; }
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bool isStore() const { return flags[IsStore]; }
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bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
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bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
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bool isInteger() const { return flags[IsInteger]; }
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bool isFloating() const { return flags[IsFloating]; }
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bool isControl() const { return flags[IsControl]; }
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bool isCall() const { return flags[IsCall]; }
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bool isReturn() const { return flags[IsReturn]; }
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bool isDirectCtrl() const { return flags[IsDirectControl]; }
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bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
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bool isCondCtrl() const { return flags[IsCondControl]; }
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bool isUncondCtrl() const { return flags[IsUncondControl]; }
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bool isThreadSync() const { return flags[IsThreadSync]; }
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//@}
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/// Operation class. Used to select appropriate function unit in issue.
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OpClass opClass() const { return _opClass; }
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};
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// forward declaration
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template <class ISA>
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class StaticInstPtr;
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/**
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* Generic yet ISA-dependent static instruction class.
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*
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* This class builds on StaticInstBase, defining fields and interfaces
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* that are generic across all ISAs but that differ in details
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* according to the specific ISA being used.
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*/
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template <class ISA>
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class StaticInst : public StaticInstBase
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{
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public:
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/// Binary machine instruction type.
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typedef typename ISA::MachInst MachInst;
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/// Memory address type.
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typedef typename ISA::Addr Addr;
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/// Logical register index type.
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typedef typename ISA::RegIndex RegIndex;
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enum {
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MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs
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MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs
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};
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/// Return logical index (architectural reg num) of i'th destination reg.
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/// Only the entries from 0 through numDestRegs()-1 are valid.
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RegIndex destRegIdx(int i) { return _destRegIdx[i]; }
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/// Return logical index (architectural reg num) of i'th source reg.
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/// Only the entries from 0 through numSrcRegs()-1 are valid.
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RegIndex srcRegIdx(int i) { return _srcRegIdx[i]; }
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/// Pointer to a statically allocated "null" instruction object.
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/// Used to give eaCompInst() and memAccInst() something to return
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/// when called on non-memory instructions.
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static StaticInstPtr<ISA> nullStaticInstPtr;
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/**
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* Memory references only: returns "fake" instruction representing
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* the effective address part of the memory operation. Used to
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* obtain the dependence info (numSrcRegs and srcRegIdx[]) for
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* just the EA computation.
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*/
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virtual StaticInstPtr<ISA> eaCompInst() { return nullStaticInstPtr; }
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/**
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* Memory references only: returns "fake" instruction representing
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* the memory access part of the memory operation. Used to
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* obtain the dependence info (numSrcRegs and srcRegIdx[]) for
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* just the memory access (not the EA computation).
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*/
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virtual StaticInstPtr<ISA> memAccInst() { return nullStaticInstPtr; }
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/// The binary machine instruction.
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const MachInst machInst;
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protected:
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/// See destRegIdx().
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RegIndex _destRegIdx[MaxInstDestRegs];
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/// See srcRegIdx().
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RegIndex _srcRegIdx[MaxInstSrcRegs];
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/**
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* Base mnemonic (e.g., "add"). Used by generateDisassembly()
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* methods. Also useful to readily identify instructions from
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* within the debugger when #cachedDisassembly has not been
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* initialized.
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*/
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const char *mnemonic;
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/**
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* String representation of disassembly (lazily evaluated via
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* disassemble()).
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*/
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std::string *cachedDisassembly;
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/**
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* Internal function to generate disassembly string.
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*/
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virtual std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) = 0;
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/// Constructor.
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StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
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: StaticInstBase(__opClass),
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machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
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{
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}
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public:
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virtual ~StaticInst()
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{
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if (cachedDisassembly)
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delete cachedDisassembly;
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}
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/**
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* Execute this instruction under SimpleCPU model.
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*/
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virtual Fault execute(SimpleCPU *cpu, ExecContext *xc,
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Trace::InstRecord *traceData) = 0;
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/**
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* Execute this instruction under detailed CPU model.
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*/
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virtual Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst,
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Trace::InstRecord *traceData) = 0;
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/**
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* Return the target address for a PC-relative branch.
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* Invalid if not a PC-relative branch (i.e. isDirectCtrl()
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* should be true).
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*/
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virtual Addr branchTarget(Addr branchPC)
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{
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panic("StaticInst::branchTarget() called on instruction "
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"that is not a PC-relative branch.");
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}
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/**
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* Return the target address for an indirect branch (jump).
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* The register value is read from the supplied execution context.
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* Invalid if not an indirect branch (i.e. isIndirectCtrl()
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* should be true).
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*/
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virtual Addr branchTarget(ExecContext *xc)
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{
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panic("StaticInst::branchTarget() called on instruction "
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"that is not an indirect branch.");
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}
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/**
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* Return true if the instruction is a control transfer, and if so,
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* return the target address as well.
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*/
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bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt);
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/**
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* Return string representation of disassembled instruction.
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* The default version of this function will call the internal
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* virtual generateDisassembly() function to get the string,
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* then cache it in #cachedDisassembly. If the disassembly
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* should not be cached, this function should be overridden directly.
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*/
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virtual const std::string &disassemble(Addr pc,
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const SymbolTable *symtab = 0)
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{
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if (!cachedDisassembly)
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cachedDisassembly =
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new std::string(generateDisassembly(pc, symtab));
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return *cachedDisassembly;
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}
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/// Decoded instruction cache type.
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/// For now we're using a generic hash_map; this seems to work
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/// pretty well.
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typedef m5::hash_map<MachInst, StaticInstPtr<ISA> > DecodeCache;
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/// A cache of decoded instruction objects.
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static DecodeCache decodeCache;
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/**
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* Dump some basic stats on the decode cache hash map.
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* Only gets called if DECODE_CACHE_HASH_STATS is defined.
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*/
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static void dumpDecodeCacheStats();
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/// Decode a machine instruction.
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/// @param mach_inst The binary instruction to decode.
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/// @retval A pointer to the corresponding StaticInst object.
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static
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StaticInstPtr<ISA> decode(MachInst mach_inst)
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{
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#ifdef DECODE_CACHE_HASH_STATS
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// Simple stats on decode hash_map. Turns out the default
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// hash function is as good as anything I could come up with.
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const int dump_every_n = 10000000;
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static int decodes_til_dump = dump_every_n;
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if (--decodes_til_dump == 0) {
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dumpDecodeCacheStats();
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decodes_til_dump = dump_every_n;
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}
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#endif
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typename DecodeCache::iterator iter = decodeCache.find(mach_inst);
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if (iter != decodeCache.end()) {
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return iter->second;
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}
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StaticInstPtr<ISA> si = ISA::decodeInst(mach_inst);
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decodeCache[mach_inst] = si;
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return si;
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}
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};
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typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
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/// Reference-counted pointer to a StaticInst object.
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/// This type should be used instead of "StaticInst<ISA> *" so that
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/// StaticInst objects can be properly reference-counted.
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template <class ISA>
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class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> >
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{
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public:
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/// Constructor.
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StaticInstPtr()
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: RefCountingPtr<StaticInst<ISA> >()
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{
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}
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/// Conversion from "StaticInst<ISA> *".
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StaticInstPtr(StaticInst<ISA> *p)
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: RefCountingPtr<StaticInst<ISA> >(p)
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{
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}
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/// Copy constructor.
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StaticInstPtr(const StaticInstPtr &r)
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: RefCountingPtr<StaticInst<ISA> >(r)
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{
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}
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/// Construct directly from machine instruction.
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/// Calls StaticInst<ISA>::decode().
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StaticInstPtr(typename ISA::MachInst mach_inst)
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: RefCountingPtr<StaticInst<ISA> >(StaticInst<ISA>::decode(mach_inst))
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{
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}
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/// Convert to pointer to StaticInstBase class.
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operator const StaticInstBasePtr()
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{
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return get();
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}
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};
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#endif // __STATIC_INST_HH__
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