689eb39d48
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem
src/python/m5/objects/BaseCPU.py:
Merge duplicate change
--HG--
extra : convert_revision : 214e57999ee78aadfc86e1f0b7198ff0d981ce16
55 lines
1.8 KiB
Python
55 lines
1.8 KiB
Python
from m5 import build_env
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from m5.config import *
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from AlphaTLB import AlphaDTB, AlphaITB
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from Bus import Bus
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class BaseCPU(SimObject):
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type = 'BaseCPU'
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abstract = True
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mem = Param.MemObject("memory")
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system = Param.System(Parent.any, "system object")
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if build_env['FULL_SYSTEM']:
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dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
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itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
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cpu_id = Param.Int(-1, "CPU identifier")
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else:
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workload = VectorParam.Process("processes to run")
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max_insts_all_threads = Param.Counter(0,
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"terminate when all threads have reached this inst count")
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max_insts_any_thread = Param.Counter(0,
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"terminate when any thread reaches this inst count")
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max_loads_all_threads = Param.Counter(0,
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"terminate when all threads have reached this load count")
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max_loads_any_thread = Param.Counter(0,
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"terminate when any thread reaches this load count")
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defer_registration = Param.Bool(False,
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"defer registration with system (for sampling)")
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clock = Param.Clock(Parent.clock, "clock speed")
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_mem_ports = []
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def connectMemPorts(self, bus):
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for p in self._mem_ports:
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exec('self.%s = bus.port' % p)
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def addPrivateSplitL1Caches(self, ic, dc):
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assert(len(self._mem_ports) == 2)
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self.icache = ic
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self.dcache = dc
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self.icache_port = ic.cpu_side
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self.dcache_port = dc.cpu_side
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self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
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# self.mem = dc
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def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
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self.addPrivateSplitL1Caches(ic, dc)
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self.toL2Bus = Bus()
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self.connectMemPorts(self.toL2Bus)
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self.l2cache = l2c
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self.l2cache.cpu_side = self.toL2Bus.port
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self._mem_ports = ['l2cache.mem_side']
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