270 lines
8.5 KiB
Text
270 lines
8.5 KiB
Text
// Copyright (c) 2006-2007 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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// Steve Reinhardt
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////////////////////////////////////////////////////////////////////
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//
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// Branch instructions
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//
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output header {{
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/**
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* Base class for branch operations.
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*/
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class Branch : public SparcStaticInst
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{
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protected:
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// Constructor
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Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
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SparcStaticInst(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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};
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/**
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* Base class for branch operations with an immediate displacement.
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*/
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class BranchDisp : public Branch
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{
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protected:
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// Constructor
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BranchDisp(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass) :
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Branch(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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int32_t disp;
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};
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/**
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* Base class for branches with n bit displacements.
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*/
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template<int bits>
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class BranchNBits : public BranchDisp
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{
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protected:
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// Constructor
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BranchNBits(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass) :
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BranchDisp(mnem, _machInst, __opClass)
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{
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disp = sext<bits + 2>((_machInst & mask(bits)) << 2);
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}
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};
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/**
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* Base class for 16bit split displacements.
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*/
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class BranchSplit : public BranchDisp
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{
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protected:
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// Constructor
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BranchSplit(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass) :
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BranchDisp(mnem, _machInst, __opClass)
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{
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disp = sext<18>((D16HI << 16) | (D16LO << 2));
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}
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};
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/**
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* Base class for branches that use an immediate and a register to
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* compute their displacements.
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*/
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class BranchImm13 : public Branch
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{
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protected:
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// Constructor
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BranchImm13(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
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Branch(mnem, _machInst, __opClass), imm(sext<13>(SIMM13))
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{
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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int32_t imm;
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};
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}};
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output decoder {{
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template class BranchNBits<19>;
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template class BranchNBits<22>;
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template class BranchNBits<30>;
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std::string Branch::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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printMnemonic(response, mnemonic);
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printRegArray(response, _srcRegIdx, _numSrcRegs);
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if(_numDestRegs && _numSrcRegs)
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response << ", ";
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printDestReg(response, 0);
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return response.str();
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}
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std::string BranchImm13::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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printMnemonic(response, mnemonic);
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printRegArray(response, _srcRegIdx, _numSrcRegs);
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if(_numSrcRegs > 0)
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response << ", ";
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ccprintf(response, "0x%x", imm);
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if (_numDestRegs > 0)
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response << ", ";
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printDestReg(response, 0);
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return response.str();
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}
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std::string BranchDisp::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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std::string symbol;
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Addr symbolAddr;
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Addr target = disp + pc;
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printMnemonic(response, mnemonic);
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ccprintf(response, "0x%x", target);
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if(symtab && symtab->findNearestSymbol(target, symbol, symbolAddr))
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{
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ccprintf(response, " <%s", symbol);
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if(symbolAddr != target)
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ccprintf(response, "+%d>", target - symbolAddr);
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else
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ccprintf(response, ">");
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}
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return response.str();
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}
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}};
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def template BranchExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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//Attempt to execute the instruction
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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NNPC = xc->readNextNPC();
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%(code)s;
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if(fault == NoFault)
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{
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//Write the resulting state to the execution context
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%(op_wb)s;
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}
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return fault;
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}
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}};
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let {{
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handle_annul = '''
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{
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if(A)
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{
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NNPC = NPC + 8;
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NPC = NPC + 4;
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}
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else
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{
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NPC = NPC;
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NNPC = NNPC;
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}
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}'''
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}};
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// Primary format for branch instructions:
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def format Branch(code, *opt_flags) {{
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(usesImm, code, immCode,
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rString, iString) = splitOutImm(code)
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iop = InstObjParams(name, Name, 'Branch', code, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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exec_output = BranchExecute.subst(iop)
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if usesImm:
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imm_iop = InstObjParams(name, Name + 'Imm', 'BranchImm' + iString,
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immCode, opt_flags)
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header_output += BasicDeclare.subst(imm_iop)
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decoder_output += BasicConstructor.subst(imm_iop)
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exec_output += BranchExecute.subst(imm_iop)
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decode_block = ROrImmDecode.subst(iop)
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else:
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decode_block = BasicDecode.subst(iop)
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}};
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// Primary format for branch instructions:
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def format BranchN(bits, code, *opt_flags) {{
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code = re.sub(r'handle_annul', handle_annul, code)
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new_opt_flags = []
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for flag in opt_flags:
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if flag == ',a':
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name += ',a'
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Name += 'Annul'
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else:
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new_opt_flags += flag
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iop = InstObjParams(name, Name, "BranchNBits<%d>" % bits, code, new_opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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exec_output = BranchExecute.subst(iop)
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decode_block = BasicDecode.subst(iop)
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}};
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// Primary format for branch instructions:
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def format BranchSplit(code, *opt_flags) {{
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code = re.sub(r'handle_annul', handle_annul, code)
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iop = InstObjParams(name, Name, 'BranchSplit', code, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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exec_output = BranchExecute.subst(iop)
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decode_block = BasicDecode.subst(iop)
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}};
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