Andrea Pellegrini 11d5ffa108 o3 cpu: fix zero reg problem ... There was an issue w/ the rename logic, which would assign a previous physical register to the ZeroReg architectural register in x86. This issue was giving problems for instructions squashed in threads w/ ID different from 0, sometimes allowing non-mispredicted instructions to obtain a value different from zero when reading the zeroReg.		2013-01-22 00:13:28 -06:00
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arch	x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch	2013-01-22 00:10:10 -06:00
base	scons: Enforce gcc >= 4.4 or clang >= 2.9 and c++0x support	2013-01-07 13:05:39 -05:00
cpu	o3 cpu: fix zero reg problem	2013-01-22 00:13:28 -06:00
dev	dev: Fix infinite recursion in DMA devices	2013-01-07 16:56:39 -05:00
doc	MEM: Put memory system document into doxygen	2012-09-25 11:49:41 -05:00
doxygen	MEM: Put memory system document into doxygen	2012-09-25 11:49:41 -05:00
kern	base: Encapsulate the underlying fields in AddrRange	2013-01-07 13:05:38 -05:00
mem	ruby: remove calls to g_system_ptr->getTime()	2013-01-17 13:10:12 -06:00
proto	scons: Address clang 3.2 compilation error	2013-01-14 10:23:56 -05:00
python	stats: Fix swig wrapping for Tick in stats	2013-01-07 16:56:36 -05:00
sim	util: add m5_fail op.	2013-01-08 08:54:12 -05:00
unittest	AddrRange: Transition from Range<T> to AddrRange	2012-09-19 06:15:44 -04:00
Doxyfile	Doxygen: Update the version of the Doxyfile	2012-10-11 06:38:42 -04:00
SConscript	scons: Remove stale compiler options	2013-01-07 13:05:39 -05:00