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gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Andreas Hansson fda338f8d3 Stats: Updates due to bus changes 
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
2012-07-09 12:35:41 -04:00

1759 lines
200 KiB
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---------- Begin Simulation Statistics ----------
sim_seconds 1.900531 # Number of seconds simulated
sim_ticks 1900530800500 # Number of ticks simulated
final_tick 1900530800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 119697 # Simulator instruction rate (inst/s)
host_op_rate 119697 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3968630665 # Simulator tick rate (ticks/s)
host_mem_usage 303044 # Number of bytes of host memory used
host_seconds 478.89 # Real time elapsed on the host
sim_insts 57321719 # Number of instructions simulated
sim_ops 57321719 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 875648 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24657536 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 107456 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 693056 # Number of bytes read from this memory
system.physmem.bytes_read::total 28984512 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 875648 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 107456 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 983104 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7921792 # Number of bytes written to this memory
system.physmem.bytes_written::total 7921792 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 13682 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 385274 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 1679 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 10829 # Number of read requests responded to by this memory
system.physmem.num_reads::total 452883 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 123778 # Number of write requests responded to by this memory
system.physmem.num_writes::total 123778 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 460739 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 12974026 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1394777 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 56540 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 364664 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 15250746 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 460739 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 56540 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 517279 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4168200 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4168200 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4168200 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 460739 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 12974026 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1394777 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 56540 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 364664 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 19418945 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 345959 # number of replacements
system.l2c.tagsinuse 65264.030293 # Cycle average of tags in use
system.l2c.total_refs 2564962 # Total number of references to valid blocks.
system.l2c.sampled_refs 411131 # Sample count of references to valid blocks.
system.l2c.avg_refs 6.238795 # Average number of references to valid blocks.
system.l2c.warmup_cycle 6370050000 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 53566.099176 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 5313.179425 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 6099.564968 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 209.813021 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 75.373703 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.817354 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.081073 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.093072 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.003201 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.001150 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.995850 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 777532 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 689515 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 314287 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 100987 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1882321 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 806312 # number of Writeback hits
system.l2c.Writeback_hits::total 806312 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 440 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 616 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 51 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 81 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 128023 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 44351 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 172374 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 777532 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 817538 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 314287 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 145338 # number of demand (read+write) hits
system.l2c.demand_hits::total 2054695 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 777532 # number of overall hits
system.l2c.overall_hits::cpu0.data 817538 # number of overall hits
system.l2c.overall_hits::cpu1.inst 314287 # number of overall hits
system.l2c.overall_hits::cpu1.data 145338 # number of overall hits
system.l2c.overall_hits::total 2054695 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 13684 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 272967 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 1696 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 861 # number of ReadReq misses
system.l2c.ReadReq_misses::total 289208 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 2867 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1568 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 4435 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 726 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 747 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1473 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 113091 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 10063 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 123154 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 13684 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 386058 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 1696 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 10924 # number of demand (read+write) misses
system.l2c.demand_misses::total 412362 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 13684 # number of overall misses
system.l2c.overall_misses::cpu0.data 386058 # number of overall misses
system.l2c.overall_misses::cpu1.inst 1696 # number of overall misses
system.l2c.overall_misses::cpu1.data 10924 # number of overall misses
system.l2c.overall_misses::total 412362 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst 728665998 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 14214168999 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 90803000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 47077499 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 15080715496 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 2584000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 19661414 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 22245414 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2793000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 314000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 3107000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 6061091997 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 549004499 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 6610096496 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 728665998 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 20275260996 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 90803000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 596081998 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 21690811992 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 728665998 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 20275260996 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 90803000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 596081998 # number of overall miss cycles
system.l2c.overall_miss_latency::total 21690811992 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 791216 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 962482 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 315983 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 101848 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2171529 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 806312 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 806312 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 3043 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 2008 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 5051 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 777 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 777 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1554 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 241114 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 54414 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 295528 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 791216 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1203596 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 315983 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 156262 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2467057 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 791216 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1203596 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 315983 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 156262 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2467057 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.017295 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.283607 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.005367 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.008454 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.133182 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942162 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780876 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.878044 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.934363 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.961390 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.947876 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.469035 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.184934 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.416725 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.017295 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.320754 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.005367 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.069908 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.167147 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.017295 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.320754 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.005367 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.069908 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.167147 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53249.488308 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52072.847630 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53539.504717 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 54677.699187 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52144.876684 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 901.290548 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12539.167092 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 5015.876888 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3847.107438 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 420.348059 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 2109.300747 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53594.821843 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54556.742423 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 53673.421050 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 53249.488308 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52518.691482 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 53539.504717 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 54566.275906 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52601.384201 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 53249.488308 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52518.691482 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 53539.504717 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 54566.275906 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52601.384201 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 82258 # number of writebacks
system.l2c.writebacks::total 82258 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst 13683 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 272967 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 1679 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 861 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 289190 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 2867 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1568 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 4435 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 726 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 747 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1473 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 113091 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 10063 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 123154 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 13683 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 386058 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 1679 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 10924 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 412344 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 13683 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 386058 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 1679 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 10924 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 412344 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 561385998 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10939069000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 69521500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 36634000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 11606610498 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 114796000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 62749500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 177545500 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 29087500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 29880000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 58967500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4695316997 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 427005999 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 5122322996 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 561385998 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 15634385997 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 69521500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 463639999 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 16728933494 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 561385998 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 15634385997 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 69521500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 463639999 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 16728933494 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 820941530 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 16650000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 837591530 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1194248500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 359420000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 1553668500 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2015190030 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 376070000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 2391260030 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.017294 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.283607 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005314 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.008454 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.133173 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942162 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.780876 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.878044 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.934363 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961390 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.947876 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.469035 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.184934 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.416725 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017294 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.320754 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005314 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.069908 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.167140 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017294 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.320754 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005314 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.069908 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.167140 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41027.990791 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40074.694011 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41406.491959 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42548.199768 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40134.895736 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.460412 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40018.813776 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.807215 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40065.426997 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40032.247115 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41518.042965 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42433.270297 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 41592.826835 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41027.990791 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40497.505548 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41406.491959 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42442.328726 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40570.333251 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41027.990791 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40497.505548 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41406.491959 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42442.328726 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40570.333251 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 41698 # number of replacements
system.iocache.tagsinuse 0.465240 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41714 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 1711281170000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide 0.465240 # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide 0.029077 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.029077 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses
system.iocache.ReadReq_misses::total 178 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses
system.iocache.demand_misses::total 41730 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses
system.iocache.overall_misses::total 41730 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21238998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21238998 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 7637775806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 7637775806 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 7659014804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 7659014804 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 7659014804 # number of overall miss cycles
system.iocache.overall_miss_latency::total 7659014804 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119320.213483 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 119320.213483 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183812.471265 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 183812.471265 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 183537.378481 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 183537.378481 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 183537.378481 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 183537.378481 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 7710000 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 7151 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 1078.170885 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11982000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11982000 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5476916000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 5476916000 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 5488898000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 5488898000 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 5488898000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 5488898000 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67314.606742 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67314.606742 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131808.721602 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 131808.721602 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131533.620896 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 131533.620896 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131533.620896 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 131533.620896 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.read_hits 8334313 # DTB read hits
system.cpu0.dtb.read_misses 29661 # DTB read misses
system.cpu0.dtb.read_acv 416 # DTB read access violations
system.cpu0.dtb.read_accesses 650050 # DTB read accesses
system.cpu0.dtb.write_hits 5360515 # DTB write hits
system.cpu0.dtb.write_misses 6017 # DTB write misses
system.cpu0.dtb.write_acv 275 # DTB write access violations
system.cpu0.dtb.write_accesses 211537 # DTB write accesses
system.cpu0.dtb.data_hits 13694828 # DTB hits
system.cpu0.dtb.data_misses 35678 # DTB misses
system.cpu0.dtb.data_acv 691 # DTB access violations
system.cpu0.dtb.data_accesses 861587 # DTB accesses
system.cpu0.itb.fetch_hits 972456 # ITB hits
system.cpu0.itb.fetch_misses 29747 # ITB misses
system.cpu0.itb.fetch_acv 802 # ITB acv
system.cpu0.itb.fetch_accesses 1002203 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.numCycles 107494535 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.BPredUnit.lookups 11769770 # Number of BP lookups
system.cpu0.BPredUnit.condPredicted 9862090 # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect 345528 # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups 8388023 # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits 5075121 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS 768289 # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect 29261 # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles 25151812 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 60423976 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 11769770 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 5843410 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 11477495 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 1678868 # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles 36441754 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 35468 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 189532 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 310248 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 196 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 7504127 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 232204 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples 74712100 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.808758 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.135218 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 63234605 84.64% 84.64% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 741221 0.99% 85.63% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 1559530 2.09% 87.72% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 686170 0.92% 88.64% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 2492076 3.34% 91.97% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 531561 0.71% 92.68% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 568906 0.76% 93.44% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 718608 0.96% 94.41% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 4179423 5.59% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 74712100 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.109492 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.562112 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 26235752 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 36073897 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 10433111 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 896014 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1073325 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 504398 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 32602 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 59387121 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 93497 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1073325 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 27172169 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 15317742 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 17291837 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 9793019 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 4064006 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 56407383 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 7139 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 656540 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 1492805 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands 37953017 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 68861567 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 68508934 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 352633 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 33050954 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 4902063 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1333181 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 200244 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 10589201 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 8773580 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 5638577 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1132250 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 738910 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 50116652 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1669804 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 48856794 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 108488 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 5944129 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 3041029 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 1132337 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 74712100 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.653934 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.297915 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 52667189 70.49% 70.49% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 10185163 13.63% 84.13% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 4563652 6.11% 90.23% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 2983683 3.99% 94.23% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 2257783 3.02% 97.25% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1142078 1.53% 98.78% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 582516 0.78% 99.56% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 283628 0.38% 99.94% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 46408 0.06% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 74712100 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 73121 11.93% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 287582 46.92% 58.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 252262 41.15% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 4467 0.01% 0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 33934109 69.46% 69.47% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 53582 0.11% 69.58% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.58% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 16546 0.03% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 2231 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.61% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 8675974 17.76% 87.37% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 5426955 11.11% 98.48% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 742930 1.52% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 48856794 # Type of FU issued
system.cpu0.iq.rate 0.454505 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 612965 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.012546 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 172645923 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 57499135 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 47860626 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 501218 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 243758 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 236014 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 49202996 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 262296 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 518056 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 1116510 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2510 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 12661 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 476371 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 18849 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 94368 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 1073325 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 10798667 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 779958 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 54837290 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 559703 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 8773580 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 5638577 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 1469305 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 544312 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 8344 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 12661 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 186183 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 327984 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 514167 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 48431427 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 8385093 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 425367 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 3050834 # number of nop insts executed
system.cpu0.iew.exec_refs 13764236 # number of memory reference insts executed
system.cpu0.iew.exec_branches 7758760 # Number of branches executed
system.cpu0.iew.exec_stores 5379143 # Number of stores executed
system.cpu0.iew.exec_rate 0.450548 # Inst execution rate
system.cpu0.iew.wb_sent 48183951 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 48096640 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 24100280 # num instructions producing a value
system.cpu0.iew.wb_consumers 32401803 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 0.447433 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.743794 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts 48294177 # The number of committed instructions
system.cpu0.commit.commitCommittedOps 48294177 # The number of committed instructions
system.cpu0.commit.commitSquashedInsts 6449436 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 537467 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 480768 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 73638775 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.655825 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.560295 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 55222738 74.99% 74.99% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 7735232 10.50% 85.50% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 4278280 5.81% 91.31% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 2283958 3.10% 94.41% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1242509 1.69% 96.09% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 524248 0.71% 96.81% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 435052 0.59% 97.40% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 385141 0.52% 97.92% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1531617 2.08% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 73638775 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 48294177 # Number of instructions committed
system.cpu0.commit.committedOps 48294177 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 12819276 # Number of memory references committed
system.cpu0.commit.loads 7657070 # Number of loads committed
system.cpu0.commit.membars 181890 # Number of memory barriers committed
system.cpu0.commit.branches 7325526 # Number of branches committed
system.cpu0.commit.fp_insts 233448 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 44748110 # Number of committed integer instructions.
system.cpu0.commit.function_calls 610965 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 1531617 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 126666255 # The number of ROB reads
system.cpu0.rob.rob_writes 110560293 # The number of ROB writes
system.cpu0.timesIdled 1221795 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 32782435 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 3693291566 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 45532520 # Number of Instructions Simulated
system.cpu0.committedOps 45532520 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 45532520 # Number of Instructions Simulated
system.cpu0.cpi 2.360830 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 2.360830 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.423580 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.423580 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 63860317 # number of integer regfile reads
system.cpu0.int_regfile_writes 34945795 # number of integer regfile writes
system.cpu0.fp_regfile_reads 117013 # number of floating regfile reads
system.cpu0.fp_regfile_writes 117648 # number of floating regfile writes
system.cpu0.misc_regfile_reads 1550179 # number of misc regfile reads
system.cpu0.misc_regfile_writes 750147 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.cpu0.icache.replacements 790628 # number of replacements
system.cpu0.icache.tagsinuse 510.000717 # Cycle average of tags in use
system.cpu0.icache.total_refs 6669453 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 791140 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 8.430180 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 23654486000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 510.000717 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.996095 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.996095 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 6669453 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 6669453 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 6669453 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 6669453 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 6669453 # number of overall hits
system.cpu0.icache.overall_hits::total 6669453 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 834673 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 834673 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 834673 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 834673 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 834673 # number of overall misses
system.cpu0.icache.overall_misses::total 834673 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13767352493 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 13767352493 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 13767352493 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 13767352493 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 13767352493 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 13767352493 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 7504126 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 7504126 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 7504126 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 7504126 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 7504126 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 7504126 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111229 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.111229 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111229 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.111229 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111229 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.111229 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16494.306744 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 16494.306744 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16494.306744 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 16494.306744 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16494.306744 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 16494.306744 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 1480996 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 9141.950617 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.writebacks::writebacks 247 # number of writebacks
system.cpu0.icache.writebacks::total 247 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43336 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 43336 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 43336 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 43336 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 43336 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 43336 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 791337 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 791337 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 791337 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 791337 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 791337 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 791337 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10689365997 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 10689365997 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10689365997 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 10689365997 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10689365997 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 10689365997 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105454 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.105454 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105454 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.105454 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13507.982057 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13507.982057 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13507.982057 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13507.982057 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 1206208 # number of replacements
system.cpu0.dcache.tagsinuse 505.878050 # Cycle average of tags in use
system.cpu0.dcache.total_refs 9822290 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 1206649 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 8.140139 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 19675000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 505.878050 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.988043 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.988043 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 6113680 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6113680 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3377171 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 3377171 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 150549 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 150549 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171656 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 171656 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 9490851 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 9490851 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 9490851 # number of overall hits
system.cpu0.dcache.overall_hits::total 9490851 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 1478314 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1478314 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1593619 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1593619 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 18637 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 18637 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4699 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 4699 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 3071933 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 3071933 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 3071933 # number of overall misses
system.cpu0.dcache.overall_misses::total 3071933 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41272950000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 41272950000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 65317405497 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 65317405497 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 315155000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 315155000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68652000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 68652000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 106590355497 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 106590355497 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 106590355497 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 106590355497 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7591994 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 7591994 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970790 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 4970790 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 169186 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 169186 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176355 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 176355 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12562784 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 12562784 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12562784 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 12562784 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.194720 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.194720 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320597 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.320597 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110157 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110157 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026645 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026645 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244526 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.244526 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244526 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.244526 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27918.933325 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 27918.933325 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40986.839073 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 40986.839073 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16910.178677 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16910.178677 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14609.917004 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14609.917004 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34698.138109 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 34698.138109 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34698.138109 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 34698.138109 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 716537144 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 178000 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 65430 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10951.201956 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 25428.571429 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 693284 # number of writebacks
system.cpu0.dcache.writebacks::total 693284 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 515563 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 515563 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1344321 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1344321 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3732 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3732 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1859884 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1859884 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1859884 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1859884 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 962751 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 962751 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249298 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 249298 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14905 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14905 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4699 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 4699 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1212049 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 1212049 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1212049 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1212049 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25942792600 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25942792600 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8699231964 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8699231964 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186934001 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186934001 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 54037501 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 54037501 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34642024564 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 34642024564 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34642024564 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 34642024564 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 918343000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 918343000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1327727998 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1327727998 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2246070998 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2246070998 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.126811 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.126811 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050153 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050153 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088098 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088098 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026645 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026645 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096479 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.096479 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096479 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.096479 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26946.523660 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26946.523660 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34894.912771 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34894.912771 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12541.697484 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12541.697484 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11499.787402 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11499.787402 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28581.373001 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28581.373001 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28581.373001 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28581.373001 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.read_hits 2499316 # DTB read hits
system.cpu1.dtb.read_misses 12569 # DTB read misses
system.cpu1.dtb.read_acv 105 # DTB read access violations
system.cpu1.dtb.read_accesses 313735 # DTB read accesses
system.cpu1.dtb.write_hits 1734639 # DTB write hits
system.cpu1.dtb.write_misses 3525 # DTB write misses
system.cpu1.dtb.write_acv 140 # DTB write access violations
system.cpu1.dtb.write_accesses 132367 # DTB write accesses
system.cpu1.dtb.data_hits 4233955 # DTB hits
system.cpu1.dtb.data_misses 16094 # DTB misses
system.cpu1.dtb.data_acv 245 # DTB access violations
system.cpu1.dtb.data_accesses 446102 # DTB accesses
system.cpu1.itb.fetch_hits 489806 # ITB hits
system.cpu1.itb.fetch_misses 8851 # ITB misses
system.cpu1.itb.fetch_acv 360 # ITB acv
system.cpu1.itb.fetch_accesses 498657 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.numCycles 22717311 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.BPredUnit.lookups 3442703 # Number of BP lookups
system.cpu1.BPredUnit.condPredicted 2849702 # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect 108899 # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups 2361843 # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits 1192387 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS 236332 # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect 10679 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 9037199 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 16321027 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 3442703 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 1428719 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 2924126 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 526603 # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles 8306285 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 28121 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 87140 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 64229 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 1963514 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 75345 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples 20778311 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.785484 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.154367 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 17854185 85.93% 85.93% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 203613 0.98% 86.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 301133 1.45% 88.36% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 225724 1.09% 89.44% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 404540 1.95% 91.39% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 151692 0.73% 92.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 164507 0.79% 92.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 309022 1.49% 94.40% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 1163895 5.60% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 20778311 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.151545 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.718440 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 8812255 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 8762880 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 2709089 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 172906 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 321180 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 151088 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 10133 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 16020033 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 29351 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 321180 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 9094333 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 882455 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 6951469 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 2594850 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 934022 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 14843152 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 114 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 83650 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 279958 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands 9660007 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 17630674 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 17422680 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 207994 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 8331005 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 1328994 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 594043 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 64597 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 2775458 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 2641121 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 1825529 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 246953 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 159017 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 12975245 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 664400 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 12700763 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 35708 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 1746535 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 829425 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 468662 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 20778311 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.611251 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.284414 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 15115816 72.75% 72.75% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 2653114 12.77% 85.52% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 1112593 5.35% 90.87% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 724594 3.49% 94.36% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 603153 2.90% 97.26% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 287847 1.39% 98.65% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 182303 0.88% 99.52% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 88112 0.42% 99.95% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 10779 0.05% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 20778311 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 3869 1.53% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 134765 53.16% 54.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 114892 45.32% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 2823 0.02% 0.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 7927502 62.42% 62.44% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 20764 0.16% 62.60% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 10543 0.08% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 1411 0.01% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 2623377 20.66% 83.35% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 1764952 13.90% 97.25% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 349391 2.75% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 12700763 # Type of FU issued
system.cpu1.iq.rate 0.559079 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 253526 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.019961 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 46169663 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 15243166 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 12341001 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 299407 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 145151 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 140846 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 12794667 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 156799 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 115193 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 347930 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 808 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 2222 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 153073 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 370 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 11635 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 321180 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 537224 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 73444 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 14366092 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 206312 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 2641121 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 1825529 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 596088 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 55197 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 6016 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 2222 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 53937 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 130013 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 183950 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 12579473 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 2523314 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 121289 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 726447 # number of nop insts executed
system.cpu1.iew.exec_refs 4269906 # number of memory reference insts executed
system.cpu1.iew.exec_branches 1887172 # Number of branches executed
system.cpu1.iew.exec_stores 1746592 # Number of stores executed
system.cpu1.iew.exec_rate 0.553740 # Inst execution rate
system.cpu1.iew.wb_sent 12515990 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 12481847 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 5700900 # num instructions producing a value
system.cpu1.iew.wb_consumers 8040202 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 0.549442 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.709049 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts 12433159 # The number of committed instructions
system.cpu1.commit.commitCommittedOps 12433159 # The number of committed instructions
system.cpu1.commit.commitSquashedInsts 1857667 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 195738 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 173364 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 20457131 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.607767 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.554530 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 15844350 77.45% 77.45% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 2122437 10.38% 87.83% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 810532 3.96% 91.79% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 497134 2.43% 94.22% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 362445 1.77% 95.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 133722 0.65% 96.64% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 129038 0.63% 97.27% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 154146 0.75% 98.03% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 403327 1.97% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 20457131 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 12433159 # Number of instructions committed
system.cpu1.commit.committedOps 12433159 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 3965647 # Number of memory references committed
system.cpu1.commit.loads 2293191 # Number of loads committed
system.cpu1.commit.membars 64658 # Number of memory barriers committed
system.cpu1.commit.branches 1777478 # Number of branches committed
system.cpu1.commit.fp_insts 139699 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 11488003 # Number of committed integer instructions.
system.cpu1.commit.function_calls 194670 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 403327 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 34238592 # The number of ROB reads
system.cpu1.rob.rob_writes 28901418 # The number of ROB writes
system.cpu1.timesIdled 230949 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 1939000 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 3778341690 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 11789199 # Number of Instructions Simulated
system.cpu1.committedOps 11789199 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 11789199 # Number of Instructions Simulated
system.cpu1.cpi 1.926960 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.926960 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.518952 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.518952 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 16196586 # number of integer regfile reads
system.cpu1.int_regfile_writes 8796247 # number of integer regfile writes
system.cpu1.fp_regfile_reads 73611 # number of floating regfile reads
system.cpu1.fp_regfile_writes 74214 # number of floating regfile writes
system.cpu1.misc_regfile_reads 699711 # number of misc regfile reads
system.cpu1.misc_regfile_writes 299448 # number of misc regfile writes
system.cpu1.icache.replacements 315447 # number of replacements
system.cpu1.icache.tagsinuse 471.003081 # Cycle average of tags in use
system.cpu1.icache.total_refs 1635327 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 315959 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 5.175757 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 1877367216000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 471.003081 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.919928 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.919928 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 1635327 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 1635327 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 1635327 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 1635327 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 1635327 # number of overall hits
system.cpu1.icache.overall_hits::total 1635327 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 328187 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 328187 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 328187 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 328187 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 328187 # number of overall misses
system.cpu1.icache.overall_misses::total 328187 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5323842998 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 5323842998 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 5323842998 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 5323842998 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 5323842998 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 5323842998 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 1963514 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 1963514 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 1963514 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 1963514 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 1963514 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 1963514 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.167143 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.167143 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.167143 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.167143 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.167143 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.167143 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16221.980145 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 16221.980145 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16221.980145 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 16221.980145 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16221.980145 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 16221.980145 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 228998 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 37 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 6189.135135 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.writebacks::writebacks 38 # number of writebacks
system.cpu1.icache.writebacks::total 38 # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12173 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 12173 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 12173 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 12173 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 12173 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 12173 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316014 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 316014 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 316014 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 316014 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 316014 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 316014 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4183208998 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 4183208998 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4183208998 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 4183208998 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4183208998 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 4183208998 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.160943 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.160943 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.160943 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.160943 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13237.416690 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13237.416690 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13237.416690 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13237.416690 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 159076 # number of replacements
system.cpu1.dcache.tagsinuse 488.854290 # Cycle average of tags in use
system.cpu1.dcache.total_refs 3388834 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 159588 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 21.234892 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 42819944000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 488.854290 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.954794 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.954794 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 2022458 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 2022458 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 1251052 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 1251052 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 49972 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 49972 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 48601 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 48601 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 3273510 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 3273510 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 3273510 # number of overall hits
system.cpu1.dcache.overall_hits::total 3273510 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 307183 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 307183 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 360837 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 360837 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8700 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 8700 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5048 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 5048 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 668020 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 668020 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 668020 # number of overall misses
system.cpu1.dcache.overall_misses::total 668020 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6372115000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 6372115000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11323925707 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 11323925707 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 121529000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 121529000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 68413000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 68413000 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 17696040707 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 17696040707 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 17696040707 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 17696040707 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 2329641 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 2329641 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1611889 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 1611889 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 58672 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 58672 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 53649 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 53649 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 3941530 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 3941530 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 3941530 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 3941530 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.131859 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.131859 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223860 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.223860 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.148282 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.148282 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094093 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094093 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.169482 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.169482 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.169482 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.169482 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20743.709776 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 20743.709776 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31382.385141 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 31382.385141 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13968.850575 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13968.850575 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13552.496038 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13552.496038 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26490.285780 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 26490.285780 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26490.285780 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 26490.285780 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 57515988 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 6825 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8427.250989 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 112743 # number of writebacks
system.cpu1.dcache.writebacks::total 112743 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 196860 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 196860 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 298722 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 298722 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1021 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1021 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 495582 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 495582 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 495582 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 495582 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 110323 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 110323 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62115 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 62115 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7679 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7679 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5048 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 5048 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 172438 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 172438 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 172438 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 172438 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1760210564 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1760210564 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1471458330 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1471458330 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 78242000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 78242000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52885501 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52885501 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3231668894 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 3231668894 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3231668894 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 3231668894 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18623000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18623000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 400648500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 400648500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 419271500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 419271500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047356 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047356 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038536 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038536 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130880 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130880 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094093 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094093 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043749 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.043749 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043749 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.043749 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15955.064347 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15955.064347 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23689.259116 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23689.259116 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10189.087121 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10189.087121 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10476.525555 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10476.525555 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18741.048342 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18741.048342 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18741.048342 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18741.048342 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 6699 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 167510 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 58590 40.24% 40.24% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 238 0.16% 40.40% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1924 1.32% 41.72% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 340 0.23% 41.96% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 84509 58.04% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 145601 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 57892 49.08% 49.08% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 238 0.20% 49.29% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1924 1.63% 50.92% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 340 0.29% 51.20% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 57552 48.80% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 117946 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1862592276000 98.01% 98.01% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 96187500 0.01% 98.02% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 394889000 0.02% 98.04% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 155178500 0.01% 98.04% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 37157854000 1.96% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1900396385000 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.988087 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31 0.681016 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.810063 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 5 2.38% 2.38% # number of syscalls executed
system.cpu0.kern.syscall::3 18 8.57% 10.95% # number of syscalls executed
system.cpu0.kern.syscall::4 3 1.43% 12.38% # number of syscalls executed
system.cpu0.kern.syscall::6 28 13.33% 25.71% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.48% 26.19% # number of syscalls executed
system.cpu0.kern.syscall::15 1 0.48% 26.67% # number of syscalls executed
system.cpu0.kern.syscall::17 9 4.29% 30.95% # number of syscalls executed
system.cpu0.kern.syscall::19 5 2.38% 33.33% # number of syscalls executed
system.cpu0.kern.syscall::20 4 1.90% 35.24% # number of syscalls executed
system.cpu0.kern.syscall::23 2 0.95% 36.19% # number of syscalls executed
system.cpu0.kern.syscall::24 4 1.90% 38.10% # number of syscalls executed
system.cpu0.kern.syscall::33 7 3.33% 41.43% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.95% 42.38% # number of syscalls executed
system.cpu0.kern.syscall::45 35 16.67% 59.05% # number of syscalls executed
system.cpu0.kern.syscall::47 4 1.90% 60.95% # number of syscalls executed
system.cpu0.kern.syscall::48 6 2.86% 63.81% # number of syscalls executed
system.cpu0.kern.syscall::54 9 4.29% 68.10% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.48% 68.57% # number of syscalls executed
system.cpu0.kern.syscall::59 4 1.90% 70.48% # number of syscalls executed
system.cpu0.kern.syscall::71 32 15.24% 85.71% # number of syscalls executed
system.cpu0.kern.syscall::73 3 1.43% 87.14% # number of syscalls executed
system.cpu0.kern.syscall::74 9 4.29% 91.43% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.48% 91.90% # number of syscalls executed
system.cpu0.kern.syscall::90 1 0.48% 92.38% # number of syscalls executed
system.cpu0.kern.syscall::92 7 3.33% 95.71% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.95% 96.67% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.95% 97.62% # number of syscalls executed
system.cpu0.kern.syscall::132 2 0.95% 98.57% # number of syscalls executed
system.cpu0.kern.syscall::144 1 0.48% 99.05% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 210 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir 439 0.29% 0.29% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.29% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.29% # number of callpals executed
system.cpu0.kern.callpal::swpctx 3076 2.00% 2.29% # number of callpals executed
system.cpu0.kern.callpal::tbi 37 0.02% 2.32% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.32% # number of callpals executed
system.cpu0.kern.callpal::swpipl 138810 90.43% 92.75% # number of callpals executed
system.cpu0.kern.callpal::rdps 6361 4.14% 96.89% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.89% # number of callpals executed
system.cpu0.kern.callpal::wrusp 3 0.00% 96.89% # number of callpals executed
system.cpu0.kern.callpal::rdusp 6 0.00% 96.90% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.90% # number of callpals executed
system.cpu0.kern.callpal::rti 4288 2.79% 99.69% # number of callpals executed
system.cpu0.kern.callpal::callsys 327 0.21% 99.90% # number of callpals executed
system.cpu0.kern.callpal::imb 146 0.10% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 153507 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 6690 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1098 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1098
system.cpu0.kern.mode_good::user 1098
system.cpu0.kern.mode_good::idle 0
system.cpu0.kern.mode_switch_good::kernel 0.164126 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.281972 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1897963397000 99.90% 99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 1861803000 0.10% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 3077 # number of times the context was actually changed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2601 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 74467 # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0 24565 38.36% 38.36% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1923 3.00% 41.36% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 439 0.69% 42.05% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31 37108 57.95% 100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total 64035 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 23886 48.07% 48.07% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1923 3.87% 51.93% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 439 0.88% 52.82% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 23447 47.18% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 49695 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1870827437000 98.44% 98.44% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 343518500 0.02% 98.46% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 182737500 0.01% 98.46% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 29176221000 1.54% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1900529914000 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.972359 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31 0.631858 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total 0.776060 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::2 3 2.59% 2.59% # number of syscalls executed
system.cpu1.kern.syscall::3 12 10.34% 12.93% # number of syscalls executed
system.cpu1.kern.syscall::4 1 0.86% 13.79% # number of syscalls executed
system.cpu1.kern.syscall::6 14 12.07% 25.86% # number of syscalls executed
system.cpu1.kern.syscall::17 6 5.17% 31.03% # number of syscalls executed
system.cpu1.kern.syscall::19 5 4.31% 35.34% # number of syscalls executed
system.cpu1.kern.syscall::20 2 1.72% 37.07% # number of syscalls executed
system.cpu1.kern.syscall::23 2 1.72% 38.79% # number of syscalls executed
system.cpu1.kern.syscall::24 2 1.72% 40.52% # number of syscalls executed
system.cpu1.kern.syscall::33 4 3.45% 43.97% # number of syscalls executed
system.cpu1.kern.syscall::45 19 16.38% 60.34% # number of syscalls executed
system.cpu1.kern.syscall::47 2 1.72% 62.07% # number of syscalls executed
system.cpu1.kern.syscall::48 4 3.45% 65.52% # number of syscalls executed
system.cpu1.kern.syscall::54 1 0.86% 66.38% # number of syscalls executed
system.cpu1.kern.syscall::59 3 2.59% 68.97% # number of syscalls executed
system.cpu1.kern.syscall::71 22 18.97% 87.93% # number of syscalls executed
system.cpu1.kern.syscall::74 7 6.03% 93.97% # number of syscalls executed
system.cpu1.kern.syscall::90 2 1.72% 95.69% # number of syscalls executed
system.cpu1.kern.syscall::92 2 1.72% 97.41% # number of syscalls executed
system.cpu1.kern.syscall::132 2 1.72% 99.14% # number of syscalls executed
system.cpu1.kern.syscall::144 1 0.86% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 116 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir 340 0.51% 0.51% # number of callpals executed
system.cpu1.kern.callpal::wrmces 1 0.00% 0.51% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.52% # number of callpals executed
system.cpu1.kern.callpal::swpctx 1824 2.74% 3.26% # number of callpals executed
system.cpu1.kern.callpal::tbi 16 0.02% 3.28% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.01% 3.29% # number of callpals executed
system.cpu1.kern.callpal::swpipl 57992 87.22% 90.51% # number of callpals executed
system.cpu1.kern.callpal::rdps 2394 3.60% 94.11% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 94.11% # number of callpals executed
system.cpu1.kern.callpal::wrusp 4 0.01% 94.12% # number of callpals executed
system.cpu1.kern.callpal::rdusp 3 0.00% 94.13% # number of callpals executed
system.cpu1.kern.callpal::whami 3 0.00% 94.13% # number of callpals executed
system.cpu1.kern.callpal::rti 3680 5.53% 99.66% # number of callpals executed
system.cpu1.kern.callpal::callsys 188 0.28% 99.95% # number of callpals executed
system.cpu1.kern.callpal::imb 34 0.05% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
system.cpu1.kern.callpal::total 66490 # number of callpals executed
system.cpu1.kern.mode_switch::kernel 2119 # number of protection mode switches
system.cpu1.kern.mode_switch::user 641 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 2717 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 1003
system.cpu1.kern.mode_good::user 641
system.cpu1.kern.mode_good::idle 362
system.cpu1.kern.mode_switch_good::kernel 0.473336 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle 0.133235 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.366259 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 7877043500 0.41% 0.41% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 912149500 0.05% 0.46% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1891740713000 99.54% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 1825 # number of times the context was actually changed
---------- End Simulation Statistics ----------
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