7846f59d0d
in the TLB Some architectures (currently only x86) require some fixing-up of physical addresses after a normal address translation. This is usually to remap devices such as the APIC, but could be used for other memory mapped devices as well. When running the CPU in a using hardware virtualization, we still need to do these address fix-ups before inserting the request into the memory system. This patch moves this patch allows that code to be used by such CPUs without doing full address translations.
132 lines
4.6 KiB
C++
132 lines
4.6 KiB
C++
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Steve Reinhardt
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* Jaidev Patwardhan
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* Korey Sewell
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*/
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#ifndef __ARCH_MIPS_TLB_HH__
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#define __ARCH_MIPS_TLB_HH__
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#include <map>
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#include "arch/mips/isa_traits.hh"
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#include "arch/mips/pagetable.hh"
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#include "arch/mips/utility.hh"
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#include "arch/mips/vtophys.hh"
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#include "base/statistics.hh"
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#include "mem/request.hh"
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#include "params/MipsTLB.hh"
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#include "sim/fault_fwd.hh"
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#include "sim/sim_object.hh"
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#include "sim/tlb.hh"
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class ThreadContext;
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/* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB
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However, to maintain compatibility with other architectures, we'll
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simply create an ITLB and DTLB that will point to the real TLB */
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namespace MipsISA {
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class TLB : public BaseTLB
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{
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protected:
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typedef std::multimap<Addr, int> PageTable;
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PageTable lookupTable; // Quick lookup into page table
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MipsISA::PTE *table; // the Page Table
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int size; // TLB Size
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int nlu; // not last used entry (for replacement)
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void nextnlu() { if (++nlu >= size) nlu = 0; }
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MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
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mutable Stats::Scalar read_hits;
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mutable Stats::Scalar read_misses;
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mutable Stats::Scalar read_acv;
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mutable Stats::Scalar read_accesses;
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mutable Stats::Scalar write_hits;
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mutable Stats::Scalar write_misses;
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mutable Stats::Scalar write_acv;
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mutable Stats::Scalar write_accesses;
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Stats::Formula hits;
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Stats::Formula misses;
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Stats::Formula accesses;
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public:
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typedef MipsTLBParams Params;
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TLB(const Params *p);
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int probeEntry(Addr vpn,uint8_t) const;
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MipsISA::PTE *getEntry(unsigned) const;
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virtual ~TLB();
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int smallPages;
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int getsize() const { return size; }
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MipsISA::PTE &index(bool advance = true);
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void insert(Addr vaddr, MipsISA::PTE &pte);
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void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
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void flushAll();
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void demapPage(Addr vaddr, uint64_t asn)
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{
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panic("demapPage unimplemented.\n");
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}
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// static helper functions... really
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static bool validVirtualAddress(Addr vaddr);
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static Fault checkCacheability(RequestPtr &req);
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// Checkpointing
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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void regStats();
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Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
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void translateTiming(RequestPtr req, ThreadContext *tc,
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Translation *translation, Mode mode);
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/** Function stub for CheckerCPU compilation issues. MIPS does not
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* support the Checker model at the moment.
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*/
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Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
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Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
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private:
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Fault translateInst(RequestPtr req, ThreadContext *tc);
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Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
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};
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}
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#endif // __MIPS_MEMORY_HH__
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