10c79efe55
SConscript:
The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
Changed Fault to Fault *
dev/ns_gige.cc:
Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
This allocates the system wide faults.
sim/faults.hh:
This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Removed the underscores from fault names.
--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
399 lines
10 KiB
C++
399 lines
10 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DEV_SINIC_HH__
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#define __DEV_SINIC_HH__
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#include "base/inet.hh"
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#include "base/statistics.hh"
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#include "dev/etherint.hh"
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#include "dev/etherpkt.hh"
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#include "dev/io_device.hh"
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#include "dev/pcidev.hh"
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#include "dev/pktfifo.hh"
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#include "dev/sinicreg.hh"
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#include "mem/bus/bus.hh"
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#include "sim/eventq.hh"
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namespace Sinic {
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class Interface;
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class Base : public PciDev
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{
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protected:
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bool rxEnable;
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bool txEnable;
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Tick clock;
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inline Tick cycles(int numCycles) const { return numCycles * clock; }
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protected:
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Tick intrDelay;
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Tick intrTick;
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bool cpuIntrEnable;
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bool cpuPendingIntr;
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void cpuIntrPost(Tick when);
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void cpuInterrupt();
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void cpuIntrClear();
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typedef EventWrapper<Base, &Base::cpuInterrupt> IntrEvent;
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friend void IntrEvent::process();
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IntrEvent *intrEvent;
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Interface *interface;
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bool cpuIntrPending() const;
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void cpuIntrAck() { cpuIntrClear(); }
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/**
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* Serialization stuff
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*/
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public:
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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/**
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* Construction/Destruction/Parameters
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*/
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public:
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struct Params : public PciDev::Params
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{
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Tick clock;
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Tick intr_delay;
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};
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Base(Params *p);
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};
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class Device : public Base
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{
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protected:
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Platform *plat;
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PhysicalMemory *physmem;
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protected:
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/** Receive State Machine States */
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enum RxState {
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rxIdle,
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rxFifoBlock,
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rxBeginCopy,
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rxCopy,
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rxCopyDone
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};
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/** Transmit State Machine states */
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enum TxState {
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txIdle,
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txFifoBlock,
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txBeginCopy,
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txCopy,
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txCopyDone
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};
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/** device register file */
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struct {
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uint32_t Config; // 0x00
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uint32_t Command; // 0x04
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uint32_t IntrStatus; // 0x08
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uint32_t IntrMask; // 0x0c
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uint32_t RxMaxCopy; // 0x10
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uint32_t TxMaxCopy; // 0x14
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uint32_t RxMaxIntr; // 0x18
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uint32_t Reserved0; // 0x1c
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uint32_t RxFifoSize; // 0x20
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uint32_t TxFifoSize; // 0x24
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uint32_t RxFifoMark; // 0x28
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uint32_t TxFifoMark; // 0x2c
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uint64_t RxData; // 0x30
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uint64_t RxDone; // 0x38
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uint64_t RxWait; // 0x40
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uint64_t TxData; // 0x48
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uint64_t TxDone; // 0x50
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uint64_t TxWait; // 0x58
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uint64_t HwAddr; // 0x60
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} regs;
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struct VirtualReg {
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uint64_t RxData;
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uint64_t RxDone;
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uint64_t TxData;
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uint64_t TxDone;
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PacketFifo::iterator rxPacket;
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int rxPacketOffset;
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int rxPacketBytes;
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uint64_t rxDoneData;
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VirtualReg()
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: RxData(0), RxDone(0), TxData(0), TxDone(0),
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rxPacketOffset(0), rxPacketBytes(0), rxDoneData(0)
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{ }
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};
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typedef std::vector<VirtualReg> VirtualRegs;
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typedef std::list<int> VirtualList;
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VirtualRegs virtualRegs;
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VirtualList rxList;
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VirtualList txList;
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uint8_t ®Data8(Addr daddr) { return *((uint8_t *)®s + daddr); }
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uint32_t ®Data32(Addr daddr) { return *(uint32_t *)®Data8(daddr); }
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uint64_t ®Data64(Addr daddr) { return *(uint64_t *)®Data8(daddr); }
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private:
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Addr addr;
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static const Addr size = Regs::Size;
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protected:
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RxState rxState;
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PacketFifo rxFifo;
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PacketFifo::iterator rxFifoPtr;
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bool rxEmpty;
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Addr rxDmaAddr;
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uint8_t *rxDmaData;
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int rxDmaLen;
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TxState txState;
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PacketFifo txFifo;
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bool txFull;
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PacketPtr txPacket;
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int txPacketOffset;
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int txPacketBytes;
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Addr txDmaAddr;
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uint8_t *txDmaData;
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int txDmaLen;
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protected:
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void reset();
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void rxKick();
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Tick rxKickTick;
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typedef EventWrapper<Device, &Device::rxKick> RxKickEvent;
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friend void RxKickEvent::process();
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void txKick();
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Tick txKickTick;
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typedef EventWrapper<Device, &Device::txKick> TxKickEvent;
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friend void TxKickEvent::process();
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/**
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* Retransmit event
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*/
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void transmit();
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void txEventTransmit()
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{
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transmit();
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if (txState == txFifoBlock)
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txKick();
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}
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typedef EventWrapper<Device, &Device::txEventTransmit> TxEvent;
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friend void TxEvent::process();
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TxEvent txEvent;
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void txDump() const;
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void rxDump() const;
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/**
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* receive address filter
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*/
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bool rxFilter(const PacketPtr &packet);
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/**
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* device configuration
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*/
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void changeConfig(uint32_t newconfig);
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void command(uint32_t command);
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/**
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* device ethernet interface
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*/
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public:
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bool recvPacket(PacketPtr packet);
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void transferDone();
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void setInterface(Interface *i) { assert(!interface); interface = i; }
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/**
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* DMA parameters
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*/
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protected:
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void rxDmaCopy();
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void rxDmaDone();
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friend class EventWrapper<Device, &Device::rxDmaDone>;
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EventWrapper<Device, &Device::rxDmaDone> rxDmaEvent;
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void txDmaCopy();
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void txDmaDone();
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friend class EventWrapper<Device, &Device::txDmaDone>;
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EventWrapper<Device, &Device::txDmaDone> txDmaEvent;
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Tick dmaReadDelay;
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Tick dmaReadFactor;
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Tick dmaWriteDelay;
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Tick dmaWriteFactor;
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/**
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* Interrupt management
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*/
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protected:
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void devIntrPost(uint32_t interrupts);
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void devIntrClear(uint32_t interrupts = Regs::Intr_All);
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void devIntrChangeMask(uint32_t newmask);
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/**
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* PCI Configuration interface
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*/
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public:
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virtual void writeConfig(int offset, int size, const uint8_t *data);
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/**
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* Memory Interface
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*/
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public:
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virtual Fault * read(MemReqPtr &req, uint8_t *data);
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virtual Fault * write(MemReqPtr &req, const uint8_t *data);
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void prepareIO(int cpu, int index);
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void prepareRead(int cpu, int index);
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void prepareWrite(int cpu, int index);
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Fault * iprRead(Addr daddr, int cpu, uint64_t &result);
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Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
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Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
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void regWrite(Addr daddr, int cpu, const uint8_t *data);
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Tick cacheAccess(MemReqPtr &req);
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protected:
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struct RegWriteData {
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Addr daddr;
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uint64_t value;
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RegWriteData(Addr da, uint64_t val) : daddr(da), value(val) {}
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};
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std::vector<std::list<RegWriteData> > writeQueue;
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bool pioDelayWrite;
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/**
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* Statistics
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*/
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private:
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Stats::Scalar<> rxBytes;
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Stats::Formula rxBandwidth;
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Stats::Scalar<> rxPackets;
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Stats::Formula rxPacketRate;
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Stats::Scalar<> rxIpPackets;
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Stats::Scalar<> rxTcpPackets;
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Stats::Scalar<> rxUdpPackets;
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Stats::Scalar<> rxIpChecksums;
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Stats::Scalar<> rxTcpChecksums;
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Stats::Scalar<> rxUdpChecksums;
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Stats::Scalar<> txBytes;
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Stats::Formula txBandwidth;
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Stats::Formula totBandwidth;
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Stats::Formula totPackets;
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Stats::Formula totBytes;
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Stats::Formula totPacketRate;
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Stats::Scalar<> txPackets;
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Stats::Formula txPacketRate;
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Stats::Scalar<> txIpPackets;
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Stats::Scalar<> txTcpPackets;
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Stats::Scalar<> txUdpPackets;
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Stats::Scalar<> txIpChecksums;
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Stats::Scalar<> txTcpChecksums;
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Stats::Scalar<> txUdpChecksums;
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public:
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virtual void regStats();
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/**
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* Serialization stuff
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*/
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public:
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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/**
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* Construction/Destruction/Parameters
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*/
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public:
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struct Params : public Base::Params
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{
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IntrControl *i;
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PhysicalMemory *pmem;
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Tick tx_delay;
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Tick rx_delay;
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HierParams *hier;
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Bus *pio_bus;
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Bus *header_bus;
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Bus *payload_bus;
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Tick pio_latency;
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bool pio_delay_write;
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PhysicalMemory *physmem;
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IntrControl *intctrl;
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bool rx_filter;
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Net::EthAddr eaddr;
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uint32_t rx_max_copy;
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uint32_t tx_max_copy;
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uint32_t rx_max_intr;
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uint32_t rx_fifo_size;
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uint32_t tx_fifo_size;
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uint32_t rx_fifo_threshold;
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uint32_t tx_fifo_threshold;
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Tick dma_read_delay;
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Tick dma_read_factor;
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Tick dma_write_delay;
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Tick dma_write_factor;
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bool dma_no_allocate;
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bool rx_thread;
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bool tx_thread;
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};
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protected:
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const Params *params() const { return (const Params *)_params; }
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public:
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Device(Params *params);
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~Device();
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};
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/*
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* Ethernet Interface for an Ethernet Device
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*/
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class Interface : public EtherInt
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{
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private:
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Device *dev;
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public:
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Interface(const std::string &name, Device *d)
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: EtherInt(name), dev(d) { dev->setInterface(this); }
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virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); }
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virtual void sendDone() { dev->transferDone(); }
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};
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/* namespace Sinic */ }
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#endif // __DEV_SINIC_HH__
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