1702 lines
198 KiB
Text
1702 lines
198 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 5.143601 # Number of seconds simulated
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sim_ticks 5143601047500 # Number of ticks simulated
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final_tick 5143601047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 255414 # Simulator instruction rate (inst/s)
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host_op_rate 507504 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 5398723492 # Simulator tick rate (ticks/s)
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host_mem_usage 908456 # Number of bytes of host memory used
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host_seconds 952.74 # Real time elapsed on the host
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sim_insts 243343656 # Number of instructions simulated
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sim_ops 483521256 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::pc.south_bridge.ide 2435392 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 488448 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 6105280 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 134592 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 1637632 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.dtb.walker 1280 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 319296 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 2611264 # Number of bytes read from this memory
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system.physmem.bytes_read::total 13733504 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 488448 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 134592 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 319296 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 942336 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 9060160 # Number of bytes written to this memory
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system.physmem.bytes_written::total 9060160 # Number of bytes written to this memory
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system.physmem.num_reads::pc.south_bridge.ide 38053 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 7632 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 95395 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 2103 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 25588 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.dtb.walker 20 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 4989 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 40801 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 214586 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 141565 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 141565 # Number of write requests responded to by this memory
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system.physmem.bw_read::pc.south_bridge.ide 473480 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 94962 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 1186966 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 26167 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 318382 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.dtb.walker 249 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 62076 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 507672 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2670017 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 94962 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 26167 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 62076 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 183205 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1761443 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1761443 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1761443 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::pc.south_bridge.ide 473480 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 94962 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 1186966 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 26167 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 318382 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.dtb.walker 249 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 62076 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 507672 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 4431460 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 90446 # Total number of read requests seen
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system.physmem.writeReqs 70433 # Total number of write requests seen
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system.physmem.cpureqs 161351 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 5788544 # Total number of bytes read from memory
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system.physmem.bytesWritten 4507712 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 5788544 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 4507712 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 472 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 5853 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 5374 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 5163 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 5410 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 5863 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 6188 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 5951 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 6069 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 4925 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 4669 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 5184 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 5694 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 5956 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 5914 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 6273 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 5934 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 4493 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 4309 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 4025 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 4097 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 4752 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 4893 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 4726 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 4839 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 3464 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 3572 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 4023 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 4337 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 4609 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 4582 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 5213 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 4499 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 5140092000000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 90446 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 70433 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 70577 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 8282 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 3161 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1284 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 1096 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 890 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 563 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 524 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 494 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 461 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 417 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 407 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 373 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 391 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 408 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 405 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 308 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 227 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 98 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 2678 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 2775 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 3060 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 3074 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 3071 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 3068 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 3068 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 3066 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 3065 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 3063 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 3061 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 3060 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::12 3059 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 3059 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::14 3058 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::15 3054 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 3052 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 3051 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::18 3046 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::19 3044 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 3040 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::21 3037 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 3035 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 439 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 311 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 30233 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 340.294645 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 151.805560 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 1124.042449 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-67 13536 44.77% 44.77% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-131 4627 15.30% 60.08% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::192-195 2854 9.44% 69.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-259 1864 6.17% 75.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::320-323 1230 4.07% 79.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-387 1007 3.33% 83.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::448-451 772 2.55% 85.63% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::512-515 598 1.98% 87.61% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::576-579 458 1.51% 89.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-643 438 1.45% 90.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::704-707 281 0.93% 91.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-771 279 0.92% 92.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::832-835 209 0.69% 93.12% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-899 207 0.68% 93.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::960-963 177 0.59% 94.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1027 236 0.78% 95.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1088-1091 132 0.44% 95.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1152-1155 98 0.32% 95.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1216-1219 103 0.34% 96.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1280-1283 81 0.27% 96.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1344-1347 87 0.29% 96.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1408-1411 80 0.26% 97.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1472-1475 236 0.78% 97.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1536-1539 88 0.29% 98.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1600-1603 47 0.16% 98.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1664-1667 40 0.13% 98.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1728-1731 31 0.10% 98.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1792-1795 30 0.10% 98.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1856-1859 19 0.06% 98.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1920-1923 16 0.05% 98.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1984-1987 8 0.03% 98.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2048-2051 13 0.04% 98.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2112-2115 5 0.02% 98.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2176-2179 8 0.03% 98.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2240-2243 4 0.01% 98.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2304-2307 5 0.02% 98.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2368-2371 9 0.03% 98.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2432-2435 4 0.01% 98.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2496-2499 3 0.01% 98.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2560-2563 4 0.01% 98.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2624-2627 2 0.01% 98.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2688-2691 4 0.01% 99.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2752-2755 4 0.01% 99.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2816-2819 2 0.01% 99.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2880-2883 4 0.01% 99.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2944-2947 4 0.01% 99.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3008-3011 2 0.01% 99.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3072-3075 5 0.02% 99.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3136-3139 1 0.00% 99.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3200-3203 2 0.01% 99.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3264-3267 2 0.01% 99.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3328-3331 2 0.01% 99.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3392-3395 5 0.02% 99.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3456-3459 7 0.02% 99.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3520-3523 2 0.01% 99.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3584-3587 3 0.01% 99.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3712-3715 1 0.00% 99.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3776-3779 6 0.02% 99.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3840-3843 2 0.01% 99.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3968-3971 2 0.01% 99.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4096-4099 12 0.04% 99.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4160-4163 1 0.00% 99.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4224-4227 1 0.00% 99.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4288-4291 2 0.01% 99.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4608-4611 2 0.01% 99.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4864-4867 1 0.00% 99.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5056-5059 3 0.01% 99.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5120-5123 2 0.01% 99.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5248-5251 1 0.00% 99.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5440-5443 1 0.00% 99.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5504-5507 1 0.00% 99.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5568-5571 1 0.00% 99.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5696-5699 1 0.00% 99.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5824-5827 1 0.00% 99.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6144-6147 3 0.01% 99.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6336-6339 1 0.00% 99.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6400-6403 1 0.00% 99.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6592-6595 2 0.01% 99.33% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6656-6659 1 0.00% 99.33% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6720-6723 4 0.01% 99.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6848-6851 4 0.01% 99.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6912-6915 2 0.01% 99.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6976-6979 1 0.00% 99.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7488-7491 2 0.01% 99.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7808-7811 1 0.00% 99.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8064-8067 2 0.01% 99.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8192-8195 29 0.10% 99.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8384-8387 2 0.01% 99.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9536-9539 3 0.01% 99.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10112-10115 2 0.01% 99.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10624-10627 2 0.01% 99.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11136-11139 2 0.01% 99.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11456-11459 2 0.01% 99.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14912-14915 15 0.05% 99.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14976-14979 11 0.04% 99.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15040-15043 7 0.02% 99.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15104-15107 2 0.01% 99.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15168-15171 6 0.02% 99.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15296-15299 3 0.01% 99.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15360-15363 3 0.01% 99.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15488-15491 4 0.01% 99.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15616-15619 2 0.01% 99.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15744-15747 2 0.01% 99.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15808-15811 3 0.01% 99.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15872-15875 5 0.02% 99.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16064-16067 2 0.01% 99.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16128-16131 5 0.02% 99.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16192-16195 2 0.01% 99.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16256-16259 3 0.01% 99.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16384-16387 21 0.07% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16448-16451 3 0.01% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16768-16771 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17024-17027 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 30233 # Bytes accessed per row activation
|
|
system.physmem.totQLat 1718746250 # Total cycles spent in queuing delays
|
|
system.physmem.totMemAccLat 3502520000 # Sum of mem lat for all requests
|
|
system.physmem.totBusLat 452100000 # Total cycles spent in databus access
|
|
system.physmem.totBankLat 1331673750 # Total cycles spent in bank access
|
|
system.physmem.avgQLat 19008.47 # Average queueing delay per request
|
|
system.physmem.avgBankLat 14727.65 # Average bank access latency per request
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
|
system.physmem.avgMemAccLat 38736.12 # Average memory access latency
|
|
system.physmem.avgRdBW 1.13 # Average achieved read bandwidth in MB/s
|
|
system.physmem.avgWrBW 0.88 # Average achieved write bandwidth in MB/s
|
|
system.physmem.avgConsumedRdBW 1.13 # Average consumed read bandwidth in MB/s
|
|
system.physmem.avgConsumedWrBW 0.88 # Average consumed write bandwidth in MB/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
|
system.physmem.busUtil 0.02 # Data bus utilization in percentage
|
|
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
|
system.physmem.avgWrQLen 0.11 # Average write queue length over time
|
|
system.physmem.readRowHits 78857 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 51763 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 87.21 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 73.49 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 31950049.42 # Average gap between requests
|
|
system.membus.throughput 6398386 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 425816 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 425816 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 5631 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 5631 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 70433 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 476 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 476 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 69519 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 69519 # Transaction distribution
|
|
system.membus.trans_dist::MessageReq 269 # Transaction distribution
|
|
system.membus.trans_dist::MessageResp 269 # Transaction distribution
|
|
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 538 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.apicbridge.master::total 538 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 197349 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312424 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498122 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 1007895 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 60171 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 60171 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::system.physmem.port 257520 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::system.bridge.slave 312424 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::system.cpu0.interrupts.pio 498122 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::system.cpu0.interrupts.int_slave 538 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1068604 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 1076 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.apicbridge.master::total 1076 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7851072 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 159641 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996241 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::total 9006954 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2445184 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::total 2445184 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::system.physmem.port 10296256 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::system.bridge.slave 159641 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::system.cpu0.interrupts.pio 996241 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::system.cpu0.interrupts.int_slave 1076 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 11453214 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 32574935 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 335808 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 770602000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 164025500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 314786000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer3.occupancy 538000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer0.occupancy 269000 # Layer occupancy (ticks)
|
|
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 1575668988 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer4.occupancy 198012000 # Layer occupancy (ticks)
|
|
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.l2c.replacements 103562 # number of replacements
|
|
system.l2c.tagsinuse 64796.800964 # Cycle average of tags in use
|
|
system.l2c.total_refs 3619781 # Total number of references to valid blocks.
|
|
system.l2c.sampled_refs 167743 # Sample count of references to valid blocks.
|
|
system.l2c.avg_refs 21.579327 # Average number of references to valid blocks.
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.occ_blocks::writebacks 51276.359665 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.itb.walker 0.126176 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.inst 1273.083994 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.data 4560.482374 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu1.inst 265.925814 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu1.data 1312.167499 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu2.dtb.walker 5.741812 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu2.inst 1370.746219 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu2.data 4732.167410 # Average occupied blocks per requestor
|
|
system.l2c.occ_percent::writebacks 0.782415 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.inst 0.019426 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.data 0.069587 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.inst 0.004058 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.data 0.020022 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu2.dtb.walker 0.000088 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu2.inst 0.020916 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu2.data 0.072207 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::total 0.988721 # Average percentage of cache occupancy
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 21527 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 11247 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 380736 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 540863 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 5306 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 2771 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 154822 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 225347 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.dtb.walker 39624 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.itb.walker 7543 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.inst 294341 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.data 531967 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 2216094 # number of ReadReq hits
|
|
system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits
|
|
system.l2c.WriteReq_hits::total 2 # number of WriteReq hits
|
|
system.l2c.Writeback_hits::writebacks 1541993 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 1541993 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 185 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 34 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu2.data 34 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 253 # number of UpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 81134 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 39930 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu2.data 50435 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 171499 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 21527 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 11249 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 380736 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 621997 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 5306 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 2771 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 154822 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 265277 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.dtb.walker 39624 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.itb.walker 7543 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 294341 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 582402 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 2387595 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 21527 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 11249 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 380736 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 621997 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 5306 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 2771 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 154822 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 265277 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.dtb.walker 39624 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.itb.walker 7543 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 294341 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 582402 # number of overall hits
|
|
system.l2c.overall_hits::total 2387595 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 7632 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 14556 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 2103 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 4151 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.dtb.walker 20 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.inst 4990 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.data 14210 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 47667 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 996 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 152 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2.data 164 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 1312 # number of UpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 81386 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 21703 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 26712 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 129801 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 7632 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 95942 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 2103 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 25854 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.dtb.walker 20 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 4990 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 40922 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 177468 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 7632 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 95942 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 2103 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 25854 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.dtb.walker 20 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 4990 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 40922 # number of overall misses
|
|
system.l2c.overall_misses::total 177468 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 168360000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 318876500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 1858500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.inst 450433500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.data 1172801993 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 2112330493 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 1963500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu2.data 2169000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 4132500 # number of UpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 1523449000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 1983970000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 3507419000 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 168360000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 1842325500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.dtb.walker 1858500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.inst 450433500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.data 3156771993 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 5619749493 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 168360000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 1842325500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.dtb.walker 1858500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.inst 450433500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.data 3156771993 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 5619749493 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 21527 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 11252 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.inst 388368 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 555419 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 5306 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 2771 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 156925 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 229498 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.dtb.walker 39644 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.itb.walker 7543 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.inst 299331 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.data 546177 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 2263761 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses)
|
|
system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 1541993 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 1541993 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 1181 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 186 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu2.data 198 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 1565 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 162520 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 61633 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2.data 77147 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 301300 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 21527 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 11254 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 388368 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 717939 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 5306 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 2771 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 156925 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 291131 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.dtb.walker 39644 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.itb.walker 7543 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.inst 299331 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.data 623324 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2565063 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 21527 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 11254 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 388368 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 717939 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 5306 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 2771 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 156925 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 291131 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.dtb.walker 39644 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.itb.walker 7543 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.inst 299331 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.data 623324 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2565063 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000444 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.019651 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.026207 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.013401 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.018087 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000504 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.inst 0.016671 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.data 0.026017 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.021057 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.843353 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.817204 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.828283 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.838339 # miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.500775 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.352133 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2.data 0.346248 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.430803 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000444 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.019651 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.133635 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.013401 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.088805 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000504 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.inst 0.016671 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.data 0.065651 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.069187 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000444 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.019651 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.133635 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.013401 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.088805 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000504 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.inst 0.016671 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.data 0.065651 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.069187 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80057.061341 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 76819.200193 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 92925 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 90267.234469 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.data 82533.567417 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 44314.315837 # average ReadReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12917.763158 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 13225.609756 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 3149.771341 # average UpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70195.318620 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74272.611560 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 27021.509850 # average ReadExReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 80057.061341 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 71258.818751 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 92925 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.inst 90267.234469 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.data 77141.195274 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 31666.269373 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 80057.061341 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 71258.818751 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 92925 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.inst 90267.234469 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.data 77141.195274 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 31666.269373 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 94898 # number of writebacks
|
|
system.l2c.writebacks::total 94898 # number of writebacks
|
|
system.l2c.ReadReq_mshr_hits::cpu2.inst 1 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
|
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 2103 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.data 4151 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 20 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.inst 4989 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.data 14210 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 25473 # number of ReadReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 152 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu2.data 164 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 316 # number of UpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 21703 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 26712 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 48415 # number of ReadExReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 2103 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 25854 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.dtb.walker 20 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.inst 4989 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.data 40922 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 73888 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 2103 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 25854 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.dtb.walker 20 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.inst 4989 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.data 40922 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 73888 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 141927001 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 266998007 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 1609750 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 388375752 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 995867746 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 1794778256 # number of ReadReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1620150 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 1740662 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 3360812 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1250022394 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1647192543 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 2897214937 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 141927001 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 1517020401 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 1609750 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.inst 388375752 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.data 2643060289 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 4691993193 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 141927001 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 1517020401 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 1609750 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.inst 388375752 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.data 2643060289 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 4691993193 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28533740000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30392173500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 58925913500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 434854000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 626965000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 1061819000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28968594000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31019138500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 59987732500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.013401 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.018087 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000504 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.016667 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.026017 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.011253 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.817204 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.828283 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.201917 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.352133 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.346248 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.160687 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.013401 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.088805 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000504 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.016667 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.065651 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.028806 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.013401 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.088805 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000504 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.016667 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.065651 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.028806 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67487.874941 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64321.370031 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 80487.500000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 77846.412508 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 70082.177762 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 70458.063675 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10658.881579 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10613.792683 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10635.481013 # average UpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57596.755932 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61664.890049 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 59841.266901 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67487.874941 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58676.429218 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 80487.500000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 77846.412508 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 64587.759371 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 63501.423682 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67487.874941 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58676.429218 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 80487.500000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 77846.412508 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 64587.759371 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 63501.423682 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.replacements 47575 # number of replacements
|
|
system.iocache.tagsinuse 0.112740 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.sampled_refs 47591 # Sample count of references to valid blocks.
|
|
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.warmup_cycle 4999844175559 # Cycle when the warmup percentage was hit.
|
|
system.iocache.occ_blocks::pc.south_bridge.ide 0.112740 # Average occupied blocks per requestor
|
|
system.iocache.occ_percent::pc.south_bridge.ide 0.007046 # Average percentage of cache occupancy
|
|
system.iocache.occ_percent::total 0.007046 # Average percentage of cache occupancy
|
|
system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 910 # number of ReadReq misses
|
|
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
|
|
system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 47630 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses
|
|
system.iocache.overall_misses::total 47630 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132357305 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 132357305 # number of ReadReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 4636265535 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::total 4636265535 # number of WriteReq miss cycles
|
|
system.iocache.demand_miss_latency::pc.south_bridge.ide 4768622840 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 4768622840 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::pc.south_bridge.ide 4768622840 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 4768622840 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
|
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145447.587912 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 145447.587912 # average ReadReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 99235.135595 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::total 99235.135595 # average WriteReq miss latency
|
|
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 100118.052488 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 100118.052488 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 100118.052488 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 100118.052488 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 62980 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 5996 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 10.503669 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 46667 # number of writebacks
|
|
system.iocache.writebacks::total 46667 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 701 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 701 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 21264 # number of WriteReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::total 21264 # number of WriteReq MSHR misses
|
|
system.iocache.demand_mshr_misses::pc.south_bridge.ide 21965 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 21965 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::pc.south_bridge.ide 21965 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 21965 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95889055 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 95889055 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3530226785 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::total 3530226785 # number of WriteReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3626115840 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 3626115840 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3626115840 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 3626115840 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.770330 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 0.770330 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.455137 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::total 0.455137 # mshr miss rate for WriteReq accesses
|
|
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.461159 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 0.461159 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.461159 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 0.461159 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 136788.951498 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 136788.951498 # average ReadReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 166018.942109 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::total 166018.942109 # average WriteReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 165086.084225 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 165086.084225 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 165086.084225 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 165086.084225 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
|
|
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
|
|
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
|
|
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
|
|
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
|
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.toL2Bus.throughput 52020310 # Throughput (bytes/s)
|
|
system.toL2Bus.trans_dist::ReadReq 1696057 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 1695532 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 5631 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 5631 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 870189 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 384 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 384 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 160044 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 138785 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 912543 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3510594 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port 23321 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port 95695 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count 4542153 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29200384 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 115384682 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port 82512 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port 359600 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size 145027178 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.data_through_bus 267476487 # Total data (bytes)
|
|
system.toL2Bus.snoop_data_through_bus 95232 # Total snoop data (bytes)
|
|
system.toL2Bus.reqLayer0.occupancy 4838788408 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 814500 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 2054232112 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 4517736918 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 13025458 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 50823334 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.throughput 1261125 # Throughput (bytes/s)
|
|
system.iobus.trans_dist::ReadReq 151553 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 151553 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 26624 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 26624 # Transaction distribution
|
|
system.iobus.trans_dist::MessageReq 269 # Transaction distribution
|
|
system.iobus.trans_dist::MessageResp 269 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 12 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 26 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 290304 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 54 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15696 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 312424 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 43930 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 43930 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 538 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 538 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.apicbridge.slave 538 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.pc.south_bridge.ide.pio 4120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 12 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 26 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 290304 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 54 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.pc.com_1.pio 15696 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.iocache.cpu_side 43930 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 356892 # Packet count per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2333 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 13 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 145152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 108 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7848 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::total 159641 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1396968 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1396968 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1076 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 1076 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.apicbridge.slave 1076 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 2333 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 13 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 145152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 108 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.pc.com_1.pio 7848 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.iocache.cpu_side 1396968 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::total 1557685 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.data_through_bus 6486722 # Total data (bytes)
|
|
system.iobus.reqLayer0.occupancy 624016 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 3409000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer5.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 24000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer9.occupancy 145153000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 43000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 11757000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 193475840 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 307064000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 26474000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer2.occupancy 269000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu0.numCycles 1771999673 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.committedInsts 74314462 # Number of instructions committed
|
|
system.cpu0.committedOps 150407349 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 138687072 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 1088594 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 14472613 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 138687072 # number of integer instructions
|
|
system.cpu0.num_fp_insts 0 # number of float instructions
|
|
system.cpu0.num_int_register_reads 341744011 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 175930003 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu0.num_mem_refs 15165282 # number of memory refs
|
|
system.cpu0.num_load_insts 10883561 # Number of load instructions
|
|
system.cpu0.num_store_insts 4281721 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 1050845405256.983643 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles -1049073405583.983643 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction -592.027991 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 593.027991 # Percentage of idle cycles
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu0.icache.replacements 844132 # number of replacements
|
|
system.cpu0.icache.tagsinuse 510.847733 # Cycle average of tags in use
|
|
system.cpu0.icache.total_refs 131418089 # Total number of references to valid blocks.
|
|
system.cpu0.icache.sampled_refs 844644 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.avg_refs 155.589916 # Average number of references to valid blocks.
|
|
system.cpu0.icache.warmup_cycle 147339657000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.occ_blocks::cpu0.inst 322.177037 # Average occupied blocks per requestor
|
|
system.cpu0.icache.occ_blocks::cpu1.inst 98.355742 # Average occupied blocks per requestor
|
|
system.cpu0.icache.occ_blocks::cpu2.inst 90.314955 # Average occupied blocks per requestor
|
|
system.cpu0.icache.occ_percent::cpu0.inst 0.629252 # Average percentage of cache occupancy
|
|
system.cpu0.icache.occ_percent::cpu1.inst 0.192101 # Average percentage of cache occupancy
|
|
system.cpu0.icache.occ_percent::cpu2.inst 0.176396 # Average percentage of cache occupancy
|
|
system.cpu0.icache.occ_percent::total 0.997749 # Average percentage of cache occupancy
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 90666828 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 38386818 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu2.inst 2364443 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 131418089 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 90666828 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 38386818 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu2.inst 2364443 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 131418089 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 90666828 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 38386818 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu2.inst 2364443 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 131418089 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 388368 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 156925 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu2.inst 315252 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 860545 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 388368 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 156925 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu2.inst 315252 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 860545 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 388368 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 156925 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu2.inst 315252 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 860545 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2194798000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4530444487 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 6725242487 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 2194798000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu2.inst 4530444487 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 6725242487 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 2194798000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu2.inst 4530444487 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 6725242487 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 91055196 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 38543743 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu2.inst 2679695 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 132278634 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 91055196 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 38543743 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu2.inst 2679695 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 132278634 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 91055196 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 38543743 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu2.inst 2679695 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 132278634 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.004265 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004071 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117645 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.006506 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.004265 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004071 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.117645 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.006506 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.004265 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004071 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.117645 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.006506 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13986.286443 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14370.866757 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 7815.096813 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13986.286443 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14370.866757 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 7815.096813 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13986.286443 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14370.866757 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 7815.096813 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 6390 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 177 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 36.101695 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 15890 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 15890 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu2.inst 15890 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 15890 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu2.inst 15890 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 15890 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 156925 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 299362 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 456287 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 156925 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu2.inst 299362 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 456287 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 156925 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu2.inst 299362 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 456287 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1880948000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3764163875 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 5645111875 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1880948000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3764163875 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 5645111875 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1880948000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3764163875 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 5645111875 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004071 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.111715 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003449 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004071 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.111715 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.003449 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004071 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.111715 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.003449 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11986.286443 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12573.953524 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12371.844639 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11986.286443 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12573.953524 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12371.844639 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11986.286443 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12573.953524 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12371.844639 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.replacements 1631841 # number of replacements
|
|
system.cpu0.dcache.tagsinuse 511.999003 # Cycle average of tags in use
|
|
system.cpu0.dcache.total_refs 19620985 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.sampled_refs 1632353 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.avg_refs 12.020062 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.occ_blocks::cpu0.data 366.099399 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.occ_blocks::cpu1.data 139.727177 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.occ_blocks::cpu2.data 6.172427 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.occ_percent::cpu0.data 0.715038 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.occ_percent::cpu1.data 0.272905 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.occ_percent::cpu2.data 0.012056 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.occ_percent::total 0.999998 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 5798796 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 2305234 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu2.data 3428925 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 11532955 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 4114382 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 1531325 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu2.data 2440703 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 8086410 # number of WriteReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 9913178 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 3836559 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu2.data 5869628 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 19619365 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 9913178 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 3836559 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu2.data 5869628 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 19619365 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 555419 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 229498 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu2.data 889034 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 1673951 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 163701 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 61819 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu2.data 89692 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 315212 # number of WriteReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 719120 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 291317 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu2.data 978726 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 1989163 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 719120 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 291317 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu2.data 978726 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 1989163 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3268485500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15010563000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 18279048500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2114115500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 2889797998 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 5003913498 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 5382601000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu2.data 17900360998 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 23282961998 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 5382601000 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu2.data 17900360998 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 23282961998 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6354215 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 2534732 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu2.data 4317959 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 13206906 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4278083 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 1593144 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu2.data 2530395 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 8401622 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 10632298 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 4127876 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu2.data 6848354 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 21608528 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 10632298 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 4127876 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu2.data 6848354 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 21608528 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.087410 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.090541 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.205892 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.126748 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.038265 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.038803 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.035446 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.037518 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.067635 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.070573 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.142914 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.092055 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.067635 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.070573 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.142914 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.092055 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14241.890997 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16884.127041 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10919.703444 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34198.474579 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32219.127659 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 15874.755714 # average WriteReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18476.783023 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 18289.450774 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 11704.904021 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18476.783023 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18289.450774 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 11704.904021 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 179212 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 11783 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.209369 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 1541993 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 1541993 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 342834 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 342834 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 12370 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 12370 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu2.data 355204 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 355204 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu2.data 355204 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 355204 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 229498 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 546200 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 775698 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 61819 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 77322 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 139141 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 291317 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu2.data 623522 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 914839 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 291317 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu2.data 623522 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 914839 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2809489500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8130780549 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 10940270049 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1990477500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2600292531 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4590770031 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4799967000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10731073080 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 15531040080 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4799967000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 10731073080 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 15531040080 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 31033142000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33153511000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 64186653000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 465277000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 664192000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1129469000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31498419000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33817703000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65316122000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.090541 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.126495 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.058734 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038803 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.030557 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016561 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.070573 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.091047 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.042337 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.070573 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.091047 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.042337 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12241.890997 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14886.086688 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14103.774986 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32198.474579 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33629.400830 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32993.654142 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16476.783023 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17210.416120 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16976.801470 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16476.783023 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17210.416120 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16976.801470 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.numCycles 2608004713 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 34942757 # Number of instructions committed
|
|
system.cpu1.committedOps 68016284 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 63114732 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 430753 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 6467325 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 63114732 # number of integer instructions
|
|
system.cpu1.num_fp_insts 0 # number of float instructions
|
|
system.cpu1.num_int_register_reads 152021040 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 81233840 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 4322210 # number of memory refs
|
|
system.cpu1.num_load_insts 2726743 # Number of load instructions
|
|
system.cpu1.num_store_insts 1595467 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 9296961839.327438 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles -6688957126.327438 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction -2.564780 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 3.564780 # Percentage of idle cycles
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu2.branchPred.lookups 28107723 # Number of BP lookups
|
|
system.cpu2.branchPred.condPredicted 28107723 # Number of conditional branches predicted
|
|
system.cpu2.branchPred.condIncorrect 253065 # Number of conditional branches incorrect
|
|
system.cpu2.branchPred.BTBLookups 25890078 # Number of BTB lookups
|
|
system.cpu2.branchPred.BTBHits 25466613 # Number of BTB hits
|
|
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu2.branchPred.BTBHitPct 98.364373 # BTB Hit Percentage
|
|
system.cpu2.branchPred.usedRAS 482621 # Number of times the RAS was used to get a target.
|
|
system.cpu2.branchPred.RASInCorrect 53231 # Number of incorrect RAS predictions.
|
|
system.cpu2.numCycles 150677905 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.fetch.icacheStallCycles 8157389 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu2.fetch.Insts 138649085 # Number of instructions fetch has processed
|
|
system.cpu2.fetch.Branches 28107723 # Number of branches that fetch encountered
|
|
system.cpu2.fetch.predictedBranches 25949234 # Number of branches that fetch has predicted taken
|
|
system.cpu2.fetch.Cycles 53330196 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu2.fetch.SquashCycles 1190060 # Number of cycles fetch has spent squashing
|
|
system.cpu2.fetch.TlbCycles 46897 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu2.fetch.BlockedCycles 22689996 # Number of cycles fetch has spent blocked
|
|
system.cpu2.fetch.MiscStallCycles 1645 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu2.fetch.PendingDrainCycles 6110 # Number of cycles fetch has spent waiting on pipes to drain
|
|
system.cpu2.fetch.PendingTrapStallCycles 10082 # Number of stall cycles due to pending traps
|
|
system.cpu2.fetch.IcacheWaitRetryStallCycles 361 # Number of stall cycles due to full MSHR
|
|
system.cpu2.fetch.CacheLines 2679696 # Number of cache lines fetched
|
|
system.cpu2.fetch.IcacheSquashes 114342 # Number of outstanding Icache misses that were squashed
|
|
system.cpu2.fetch.ItlbSquashes 1368 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu2.fetch.rateDist::samples 85168083 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::mean 3.213895 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::stdev 3.414010 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::0 31941663 37.50% 37.50% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::1 506826 0.60% 38.10% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::2 23646883 27.76% 65.86% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::3 259157 0.30% 66.17% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::4 526154 0.62% 66.79% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::5 751269 0.88% 67.67% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::6 273870 0.32% 67.99% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::7 459070 0.54% 68.53% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::8 26803191 31.47% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::total 85168083 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.branchRate 0.186542 # Number of branch fetches per cycle
|
|
system.cpu2.fetch.rate 0.920169 # Number of inst fetches per cycle
|
|
system.cpu2.decode.IdleCycles 9520844 # Number of cycles decode is idle
|
|
system.cpu2.decode.BlockedCycles 21607924 # Number of cycles decode is blocked
|
|
system.cpu2.decode.RunCycles 39424228 # Number of cycles decode is running
|
|
system.cpu2.decode.UnblockCycles 1229084 # Number of cycles decode is unblocking
|
|
system.cpu2.decode.SquashCycles 928772 # Number of cycles decode is squashing
|
|
system.cpu2.decode.DecodedInsts 273051293 # Number of instructions handled by decode
|
|
system.cpu2.decode.SquashedInsts 4 # Number of squashed instructions handled by decode
|
|
system.cpu2.rename.SquashCycles 928772 # Number of cycles rename is squashing
|
|
system.cpu2.rename.IdleCycles 10439907 # Number of cycles rename is idle
|
|
system.cpu2.rename.BlockCycles 13089260 # Number of cycles rename is blocking
|
|
system.cpu2.rename.serializeStallCycles 3699901 # count of cycles rename stalled for serializing inst
|
|
system.cpu2.rename.RunCycles 39570553 # Number of cycles rename is running
|
|
system.cpu2.rename.UnblockCycles 4982521 # Number of cycles rename is unblocking
|
|
system.cpu2.rename.RenamedInsts 272244708 # Number of instructions processed by rename
|
|
system.cpu2.rename.ROBFullEvents 6270 # Number of times rename has blocked due to ROB full
|
|
system.cpu2.rename.IQFullEvents 2417106 # Number of times rename has blocked due to IQ full
|
|
system.cpu2.rename.LSQFullEvents 1932594 # Number of times rename has blocked due to LSQ full
|
|
system.cpu2.rename.FullRegisterEvents 1355 # Number of times there has been no free registers
|
|
system.cpu2.rename.RenamedOperands 325535285 # Number of destination operands rename has renamed
|
|
system.cpu2.rename.RenameLookups 590374943 # Number of register rename lookups that rename has made
|
|
system.cpu2.rename.int_rename_lookups 590374855 # Number of integer rename lookups
|
|
system.cpu2.rename.fp_rename_lookups 88 # Number of floating rename lookups
|
|
system.cpu2.rename.CommittedMaps 317221539 # Number of HB maps that are committed
|
|
system.cpu2.rename.UndoneMaps 8313746 # Number of HB maps that are undone due to squashing
|
|
system.cpu2.rename.serializingInsts 122579 # count of serializing insts renamed
|
|
system.cpu2.rename.tempSerializingInsts 123510 # count of temporary serializing insts renamed
|
|
system.cpu2.rename.skidInsts 10816950 # count of insts added to the skid buffer
|
|
system.cpu2.memDep0.insertedLoads 5506267 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.insertedStores 2968253 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.conflictingLoads 324837 # Number of conflicting loads.
|
|
system.cpu2.memDep0.conflictingStores 268098 # Number of conflicting stores.
|
|
system.cpu2.iq.iqInstsAdded 270840712 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu2.iq.iqNonSpecInstsAdded 382144 # Number of non-speculative instructions added to the IQ
|
|
system.cpu2.iq.iqInstsIssued 269680817 # Number of instructions issued
|
|
system.cpu2.iq.iqSquashedInstsIssued 48233 # Number of squashed instructions issued
|
|
system.cpu2.iq.iqSquashedInstsExamined 5882884 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu2.iq.iqSquashedOperandsExamined 8996381 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu2.iq.iqSquashedNonSpecRemoved 45929 # Number of squashed non-spec instructions that were removed
|
|
system.cpu2.iq.issued_per_cycle::samples 85168083 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::mean 3.166454 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::stdev 2.381789 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::0 23491447 27.58% 27.58% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::1 5639421 6.62% 34.20% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::2 3592727 4.22% 38.42% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::3 2433201 2.86% 41.28% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::4 24826332 29.15% 70.43% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::5 1184872 1.39% 71.82% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::6 23718098 27.85% 99.67% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::7 237817 0.28% 99.95% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::8 44168 0.05% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::total 85168083 # Number of insts issued each cycle
|
|
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntAlu 103037 31.19% 31.19% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntMult 241 0.07% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntDiv 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatMult 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMult 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShift 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 31.26% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemRead 181800 55.03% 86.29% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemWrite 45300 13.71% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.FU_type_0::No_OpClass 57001 0.02% 0.02% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntAlu 260895656 96.74% 96.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntMult 47542 0.02% 96.78% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntDiv 43696 0.02% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.80% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemRead 5855050 2.17% 98.97% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemWrite 2781872 1.03% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::total 269680817 # Type of FU issued
|
|
system.cpu2.iq.rate 1.789783 # Inst issue rate
|
|
system.cpu2.iq.fu_busy_cnt 330378 # FU busy when requested
|
|
system.cpu2.iq.fu_busy_rate 0.001225 # FU busy rate (busy events/executed inst)
|
|
system.cpu2.iq.int_inst_queue_reads 624940807 # Number of integer instruction queue reads
|
|
system.cpu2.iq.int_inst_queue_writes 277108342 # Number of integer instruction queue writes
|
|
system.cpu2.iq.int_inst_queue_wakeup_accesses 268465757 # Number of integer instruction queue wakeup accesses
|
|
system.cpu2.iq.fp_inst_queue_reads 40 # Number of floating instruction queue reads
|
|
system.cpu2.iq.fp_inst_queue_writes 38 # Number of floating instruction queue writes
|
|
system.cpu2.iq.fp_inst_queue_wakeup_accesses 14 # Number of floating instruction queue wakeup accesses
|
|
system.cpu2.iq.int_alu_accesses 269954173 # Number of integer alu accesses
|
|
system.cpu2.iq.fp_alu_accesses 21 # Number of floating point alu accesses
|
|
system.cpu2.iew.lsq.thread0.forwLoads 584645 # Number of loads that had data forwarded from stores
|
|
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.squashedLoads 814531 # Number of loads squashed
|
|
system.cpu2.iew.lsq.thread0.ignoredResponses 6351 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu2.iew.lsq.thread0.memOrderViolation 3024 # Number of memory ordering violations
|
|
system.cpu2.iew.lsq.thread0.squashedStores 433740 # Number of stores squashed
|
|
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu2.iew.lsq.thread0.rescheduledLoads 655738 # Number of loads that were rescheduled
|
|
system.cpu2.iew.lsq.thread0.cacheBlocked 10426 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu2.iew.iewSquashCycles 928772 # Number of cycles IEW is squashing
|
|
system.cpu2.iew.iewBlockCycles 8598252 # Number of cycles IEW is blocking
|
|
system.cpu2.iew.iewUnblockCycles 798569 # Number of cycles IEW is unblocking
|
|
system.cpu2.iew.iewDispatchedInsts 271222856 # Number of instructions dispatched to IQ
|
|
system.cpu2.iew.iewDispSquashedInsts 58264 # Number of squashed instructions skipped by dispatch
|
|
system.cpu2.iew.iewDispLoadInsts 5506267 # Number of dispatched load instructions
|
|
system.cpu2.iew.iewDispStoreInsts 2968253 # Number of dispatched store instructions
|
|
system.cpu2.iew.iewDispNonSpecInsts 206333 # Number of dispatched non-speculative instructions
|
|
system.cpu2.iew.iewIQFullEvents 621407 # Number of times the IQ has become full, causing a stall
|
|
system.cpu2.iew.iewLSQFullEvents 3570 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu2.iew.memOrderViolationEvents 3024 # Number of memory order violations
|
|
system.cpu2.iew.predictedTakenIncorrect 146514 # Number of branches that were predicted taken incorrectly
|
|
system.cpu2.iew.predictedNotTakenIncorrect 137704 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu2.iew.branchMispredicts 284218 # Number of branch mispredicts detected at execute
|
|
system.cpu2.iew.iewExecutedInsts 269282728 # Number of executed instructions
|
|
system.cpu2.iew.iewExecLoadInsts 5768116 # Number of load instructions executed
|
|
system.cpu2.iew.iewExecSquashedInsts 398089 # Number of squashed instructions skipped in execute
|
|
system.cpu2.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu2.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu2.iew.exec_refs 8495654 # number of memory reference insts executed
|
|
system.cpu2.iew.exec_branches 27379135 # Number of branches executed
|
|
system.cpu2.iew.exec_stores 2727538 # Number of stores executed
|
|
system.cpu2.iew.exec_rate 1.787141 # Inst execution rate
|
|
system.cpu2.iew.wb_sent 269160909 # cumulative count of insts sent to commit
|
|
system.cpu2.iew.wb_count 268465771 # cumulative count of insts written-back
|
|
system.cpu2.iew.wb_producers 209852405 # num instructions producing a value
|
|
system.cpu2.iew.wb_consumers 343221010 # num instructions consuming a value
|
|
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu2.iew.wb_rate 1.781720 # insts written-back per cycle
|
|
system.cpu2.iew.wb_fanout 0.611421 # average fanout of values written-back
|
|
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu2.commit.commitSquashedInsts 6125563 # The number of squashed insts skipped by commit
|
|
system.cpu2.commit.commitNonSpecStalls 336215 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu2.commit.branchMispredicts 254201 # The number of times a branch was mispredicted
|
|
system.cpu2.commit.committed_per_cycle::samples 84239311 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::mean 3.146959 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::stdev 2.869440 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::0 28027655 33.27% 33.27% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::1 3948624 4.69% 37.96% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::2 1090324 1.29% 39.25% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::3 24397189 28.96% 68.21% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::4 757994 0.90% 69.11% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::5 507340 0.60% 69.72% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::6 301970 0.36% 70.08% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::7 23269432 27.62% 97.70% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::8 1938783 2.30% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::total 84239311 # Number of insts commited each cycle
|
|
system.cpu2.commit.committedInsts 134086437 # Number of instructions committed
|
|
system.cpu2.commit.committedOps 265097623 # Number of ops (including micro ops) committed
|
|
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu2.commit.refs 7226249 # Number of memory references committed
|
|
system.cpu2.commit.loads 4691736 # Number of loads committed
|
|
system.cpu2.commit.membars 162513 # Number of memory barriers committed
|
|
system.cpu2.commit.branches 27101249 # Number of branches committed
|
|
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu2.commit.int_insts 241753447 # Number of committed integer instructions.
|
|
system.cpu2.commit.function_calls 394614 # Number of function calls committed.
|
|
system.cpu2.commit.bw_lim_events 1938783 # number cycles where commit BW limit reached
|
|
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu2.rob.rob_reads 353502675 # The number of ROB reads
|
|
system.cpu2.rob.rob_writes 543377618 # The number of ROB writes
|
|
system.cpu2.timesIdled 448607 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu2.idleCycles 65509822 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu2.quiesceCycles 4919608430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu2.committedInsts 134086437 # Number of Instructions Simulated
|
|
system.cpu2.committedOps 265097623 # Number of Ops (including micro ops) Simulated
|
|
system.cpu2.committedInsts_total 134086437 # Number of Instructions Simulated
|
|
system.cpu2.cpi 1.123737 # CPI: Cycles Per Instruction
|
|
system.cpu2.cpi_total 1.123737 # CPI: Total CPI of All Threads
|
|
system.cpu2.ipc 0.889888 # IPC: Instructions Per Cycle
|
|
system.cpu2.ipc_total 0.889888 # IPC: Total IPC of All Threads
|
|
system.cpu2.int_regfile_reads 494284042 # number of integer regfile reads
|
|
system.cpu2.int_regfile_writes 320739139 # number of integer regfile writes
|
|
system.cpu2.fp_regfile_reads 62606 # number of floating regfile reads
|
|
system.cpu2.fp_regfile_writes 62592 # number of floating regfile writes
|
|
system.cpu2.misc_regfile_reads 86693613 # number of misc regfile reads
|
|
system.cpu2.misc_regfile_writes 110320 # number of misc regfile writes
|
|
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|