0fcb376e5f
This patch changes the name of a bunch of packet flags and MSHR member functions and variables to make the coherency protocol easier to understand. In addition the patch adds and updates lots of descriptions, explicitly spelling out assumptions. The following name changes are made: * the packet memInhibit flag is renamed to cacheResponding * the packet sharedAsserted flag is renamed to hasSharers * the packet NeedsExclusive attribute is renamed to NeedsWritable * the packet isSupplyExclusive is renamed responderHadWritable * the MSHR pendingDirty is renamed to pendingModified The cache states, Modified, Owned, Exclusive, Shared are also called out in the cache and MSHR code to make it easier to understand.
87 lines
3.4 KiB
C++
87 lines
3.4 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Andreas Hansson
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*/
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#include "mem/mem_object.hh"
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#include "mem/tport.hh"
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SimpleTimingPort::SimpleTimingPort(const std::string& _name,
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MemObject* _owner) :
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QueuedSlavePort(_name, _owner, queueImpl), queueImpl(*_owner, *this)
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{
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}
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void
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SimpleTimingPort::recvFunctional(PacketPtr pkt)
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{
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if (!respQueue.checkFunctional(pkt)) {
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// do an atomic access and throw away the returned latency
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recvAtomic(pkt);
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}
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}
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bool
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SimpleTimingPort::recvTimingReq(PacketPtr pkt)
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{
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// the SimpleTimingPort should not be used anywhere where there is
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// a need to deal with snoop responses and their flow control
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// requirements
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if (pkt->cacheResponding())
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panic("SimpleTimingPort should never see packets with the "
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"cacheResponding flag set\n");
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bool needsResponse = pkt->needsResponse();
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Tick latency = recvAtomic(pkt);
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// turn packet around to go back to requester if response expected
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if (needsResponse) {
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// recvAtomic() should already have turned packet into
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// atomic response
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assert(pkt->isResponse());
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schedTimingResp(pkt, curTick() + latency);
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} else {
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// queue the packet for deletion
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pendingDelete.reset(pkt);
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}
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return true;
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}
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