0fcb376e5f
This patch changes the name of a bunch of packet flags and MSHR member functions and variables to make the coherency protocol easier to understand. In addition the patch adds and updates lots of descriptions, explicitly spelling out assumptions. The following name changes are made: * the packet memInhibit flag is renamed to cacheResponding * the packet sharedAsserted flag is renamed to hasSharers * the packet NeedsExclusive attribute is renamed to NeedsWritable * the packet isSupplyExclusive is renamed responderHadWritable * the MSHR pendingDirty is renamed to pendingModified The cache states, Modified, Owned, Exclusive, Shared are also called out in the cache and MSHR code to make it easier to understand.
330 lines
10 KiB
C++
330 lines
10 KiB
C++
/*
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* Copyright (c) 2012-2013, 2015 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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*/
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/**
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* @file
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* Miss Status and Handling Register (MSHR) declaration.
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*/
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#ifndef __MEM_CACHE_MSHR_HH__
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#define __MEM_CACHE_MSHR_HH__
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#include <list>
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#include "base/printable.hh"
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#include "mem/packet.hh"
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class CacheBlk;
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class MSHRQueue;
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/**
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* Miss Status and handling Register. This class keeps all the information
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* needed to handle a cache miss including a list of target requests.
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* @sa \ref gem5MemorySystem "gem5 Memory System"
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*/
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class MSHR : public Packet::SenderState, public Printable
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{
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/**
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* Consider the MSHRQueue a friend to avoid making everything public
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*/
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friend class MSHRQueue;
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private:
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/** Cycle when ready to issue */
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Tick readyTime;
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/** True if the request is uncacheable */
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bool _isUncacheable;
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/** Flag set by downstream caches */
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bool downstreamPending;
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/**
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* Here we use one flag to track both if:
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*
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* 1. We are going to become owner or not, i.e., we will get the
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* block in an ownership state (Owned or Modified) with BlkDirty
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* set. This determines whether or not we are going to become the
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* responder and ordering point for future requests that we snoop.
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*
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* 2. We know that we are going to get a writable block, i.e. we
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* will get the block in writable state (Exclusive or Modified
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* state) with BlkWritable set. That determines whether additional
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* targets with needsWritable set will be able to be satisfied, or
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* if not should be put on the deferred list to possibly wait for
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* another request that does give us writable access.
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*
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* Condition 2 is actually just a shortcut that saves us from
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* possibly building a deferred target list and calling
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* promoteWritable() every time we get a writable block. Condition
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* 1, tracking ownership, is what is important. However, we never
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* receive ownership without marking the block dirty, and
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* consequently use pendingModified to track both ownership and
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* writability rather than having separate pendingDirty and
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* pendingWritable flags.
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*/
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bool pendingModified;
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/** Did we snoop an invalidate while waiting for data? */
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bool postInvalidate;
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/** Did we snoop a read while waiting for data? */
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bool postDowngrade;
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public:
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class Target {
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public:
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enum Source {
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FromCPU,
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FromSnoop,
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FromPrefetcher
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};
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const Tick recvTime; //!< Time when request was received (for stats)
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const Tick readyTime; //!< Time when request is ready to be serviced
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const Counter order; //!< Global order (for memory consistency mgmt)
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const PacketPtr pkt; //!< Pending request packet.
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const Source source; //!< Request from cpu, memory, or prefetcher?
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const bool markedPending; //!< Did we mark upstream MSHR
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//!< as downstreamPending?
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Target(PacketPtr _pkt, Tick _readyTime, Counter _order,
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Source _source, bool _markedPending)
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: recvTime(curTick()), readyTime(_readyTime), order(_order),
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pkt(_pkt), source(_source), markedPending(_markedPending)
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{}
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};
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class TargetList : public std::list<Target> {
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public:
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bool needsWritable;
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bool hasUpgrade;
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TargetList();
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void resetFlags() { needsWritable = hasUpgrade = false; }
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bool isReset() const { return !needsWritable && !hasUpgrade; }
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void add(PacketPtr pkt, Tick readyTime, Counter order,
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Target::Source source, bool markPending);
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void replaceUpgrades();
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void clearDownstreamPending();
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bool checkFunctional(PacketPtr pkt);
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void print(std::ostream &os, int verbosity,
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const std::string &prefix) const;
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};
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/** A list of MSHRs. */
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typedef std::list<MSHR *> List;
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/** MSHR list iterator. */
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typedef List::iterator Iterator;
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/** MSHR list const_iterator. */
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typedef List::const_iterator ConstIterator;
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/** Pointer to queue containing this MSHR. */
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MSHRQueue *queue;
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/** Order number assigned by the miss queue. */
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Counter order;
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/** Block aligned address of the MSHR. */
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Addr blkAddr;
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/** Block size of the cache. */
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unsigned blkSize;
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/** True if the request targets the secure memory space. */
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bool isSecure;
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/** True if the request has been sent to the bus. */
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bool inService;
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/** True if the request is just a simple forward from an upper level */
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bool isForward;
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/** Keep track of whether we should allocate on fill or not */
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bool allocOnFill;
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/** The pending* and post* flags are only valid if inService is
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* true. Using the accessor functions lets us detect if these
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* flags are accessed improperly.
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*/
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/** True if we need to get a writable copy of the block. */
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bool needsWritable() const { return targets.needsWritable; }
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bool isPendingModified() const {
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assert(inService); return pendingModified;
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}
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bool hasPostInvalidate() const {
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assert(inService); return postInvalidate;
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}
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bool hasPostDowngrade() const {
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assert(inService); return postDowngrade;
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}
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private:
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/** Data buffer (if needed). Currently used only for pending
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* upgrade handling. */
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uint8_t *data;
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/**
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* Pointer to this MSHR on the ready list.
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* @sa MissQueue, MSHRQueue::readyList
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*/
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Iterator readyIter;
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/**
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* Pointer to this MSHR on the allocated list.
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* @sa MissQueue, MSHRQueue::allocatedList
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*/
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Iterator allocIter;
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/** List of all requests that match the address */
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TargetList targets;
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TargetList deferredTargets;
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public:
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bool isUncacheable() const { return _isUncacheable; }
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/**
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* Allocate a miss to this MSHR.
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* @param blk_addr The address of the block.
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* @param blk_size The number of bytes to request.
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* @param pkt The original miss.
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* @param when_ready When should the MSHR be ready to act upon.
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* @param _order The logical order of this MSHR
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* @param alloc_on_fill Should the cache allocate a block on fill
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*/
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void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
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Tick when_ready, Counter _order, bool alloc_on_fill);
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bool markInService(bool pending_modified_resp);
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void clearDownstreamPending();
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/**
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* Mark this MSHR as free.
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*/
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void deallocate();
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/**
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* Add a request to the list of targets.
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* @param target The target.
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*/
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void allocateTarget(PacketPtr target, Tick when, Counter order,
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bool alloc_on_fill);
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bool handleSnoop(PacketPtr target, Counter order);
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/** A simple constructor. */
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MSHR();
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/**
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* Returns the current number of allocated targets.
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* @return The current number of allocated targets.
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*/
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int getNumTargets() const
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{ return targets.size() + deferredTargets.size(); }
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/**
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* Returns true if there are targets left.
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* @return true if there are targets
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*/
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bool hasTargets() const { return !targets.empty(); }
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/**
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* Returns a reference to the first target.
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* @return A pointer to the first target.
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*/
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Target *getTarget()
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{
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assert(hasTargets());
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return &targets.front();
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}
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/**
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* Pop first target.
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*/
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void popTarget()
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{
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targets.pop_front();
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}
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bool isForwardNoResponse() const
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{
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if (getNumTargets() != 1)
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return false;
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const Target *tgt = &targets.front();
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return tgt->source == Target::FromCPU && !tgt->pkt->needsResponse();
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}
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bool promoteDeferredTargets();
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void promoteWritable();
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bool checkFunctional(PacketPtr pkt);
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/**
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* Prints the contents of this MSHR for debugging.
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*/
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void print(std::ostream &os,
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int verbosity = 0,
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const std::string &prefix = "") const;
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/**
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* A no-args wrapper of print(std::ostream...) meant to be
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* invoked from DPRINTFs avoiding string overheads in fast mode
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*
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* @return string with mshr fields + [deferred]targets
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*/
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std::string print() const;
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};
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#endif // __MEM_CACHE_MSHR_HH__
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