625854785b
Some subset of UpgradeReq messages shifted to the new SCUpgradeReq type. Other than that there are no significant differences.
847 lines
95 KiB
Text
847 lines
95 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 205161 # Simulator instruction rate (inst/s)
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host_mem_usage 276364 # Number of bytes of host memory used
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host_seconds 258.74 # Real time elapsed on the host
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host_tick_rate 7217130781 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 53083414 # Number of instructions simulated
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sim_seconds 1.867360 # Number of seconds simulated
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sim_ticks 1867360295500 # Number of ticks simulated
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 6774596 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 12988394 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 41867 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 814870 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 12133144 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 14563531 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 1033178 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 8461193 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 999873 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle::samples 100508484 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 0.559927 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 1.327303 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0 76371825 75.99% 75.99% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 10652369 10.60% 86.58% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 5995069 5.96% 92.55% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 2948172 2.93% 95.48% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 2094039 2.08% 97.57% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 649751 0.65% 98.21% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 415244 0.41% 98.62% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 382142 0.38% 99.01% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 999873 0.99% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 100508484 # Number of insts commited each cycle
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system.cpu.commit.COM:count 56277376 # Number of instructions committed
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system.cpu.commit.COM:loads 9307406 # Number of loads committed
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system.cpu.commit.COM:membars 227986 # Number of memory barriers committed
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system.cpu.commit.COM:refs 15698987 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 773341 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 56277376 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 667767 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 9507253 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 53083414 # Number of Instructions Simulated
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system.cpu.committedInsts_total 53083414 # Number of Instructions Simulated
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system.cpu.cpi 2.579204 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 2.579204 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses::0 214827 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 214827 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15515.595548 # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11814.625753 # average LoadLockedReq mshr miss latency
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system.cpu.dcache.LoadLockedReq_hits::0 192545 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 192545 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_latency 345718500 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103721 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses::0 22282 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_misses::total 22282 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_hits 4847 # number of LoadLockedReq MSHR hits
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system.cpu.dcache.LoadLockedReq_mshr_miss_latency 205988000 # number of LoadLockedReq MSHR miss cycles
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081158 # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_misses 17435 # number of LoadLockedReq MSHR misses
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system.cpu.dcache.ReadReq_accesses::0 9344739 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 9344739 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency::0 23910.895806 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22793.768876 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.cpu.dcache.ReadReq_hits::0 7810277 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 7810277 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 36690361000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate::0 0.164206 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses::0 1534462 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 1534462 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 450067 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 24717449000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116043 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 1084395 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904961500 # number of ReadReq MSHR uncacheable cycles
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system.cpu.dcache.StoreCondReq_accesses::0 219814 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::total 219814 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56332.344016 # average StoreCondReq miss latency
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system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
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system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
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system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53332.344016 # average StoreCondReq mshr miss latency
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system.cpu.dcache.StoreCondReq_hits::0 189827 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 189827 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_miss_latency 1689238000 # number of StoreCondReq miss cycles
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system.cpu.dcache.StoreCondReq_miss_rate::0 0.136420 # miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_misses::0 29987 # number of StoreCondReq misses
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system.cpu.dcache.StoreCondReq_misses::total 29987 # number of StoreCondReq misses
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system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599277000 # number of StoreCondReq MSHR miss cycles
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system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.136420 # mshr miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_mshr_misses 29987 # number of StoreCondReq MSHR misses
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system.cpu.dcache.WriteReq_accesses::0 6156609 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 6156609 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency::0 49095.565499 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54537.318055 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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system.cpu.dcache.WriteReq_hits::0 3926536 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 3926536 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 109486695038 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate::0 0.362224 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses::0 2230073 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 2230073 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1833805 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 21611393951 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.064365 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 396268 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235673497 # number of WriteReq MSHR uncacheable cycles
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 9968.474051 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 28333.333333 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 8.834980 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 138443 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 1380065453 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 85000 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses::0 15501348 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 15501348 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency::0 38830.043030 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 31289.255523 # average overall mshr miss latency
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system.cpu.dcache.demand_hits::0 11736813 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 11736813 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 146177056038 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate::0 0.242852 # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
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system.cpu.dcache.demand_misses::0 3764535 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 3764535 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2283872 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 46328842951 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate::0 0.095518 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 1480663 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy
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system.cpu.dcache.occ_%::1 -0.019112 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 511.995421 # Average occupied blocks per context
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system.cpu.dcache.occ_blocks::1 -9.785268 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses::0 15501348 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 15501348 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency::0 38830.043030 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 31289.255523 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits::0 11736813 # number of overall hits
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system.cpu.dcache.overall_hits::1 0 # number of overall hits
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system.cpu.dcache.overall_hits::total 11736813 # number of overall hits
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system.cpu.dcache.overall_miss_latency 146177056038 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate::0 0.242852 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
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system.cpu.dcache.overall_misses::0 3764535 # number of overall misses
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system.cpu.dcache.overall_misses::1 0 # number of overall misses
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system.cpu.dcache.overall_misses::total 3764535 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2283872 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 46328842951 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate::0 0.095518 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 1480663 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 2140634997 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 1401152 # number of replacements
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system.cpu.dcache.sampled_refs 1401664 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 507.102797 # Cycle average of tags in use
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system.cpu.dcache.total_refs 12383673 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 21394000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 430200 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 48440098 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 42540 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 615090 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 72709786 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 37935584 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 12980555 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 1639247 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 136073 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 1152246 # Number of cycles decode is unblocking
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system.cpu.dtb.data_accesses 1232975 # DTB accesses
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system.cpu.dtb.data_acv 823 # DTB access violations
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system.cpu.dtb.data_hits 16785642 # DTB hits
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system.cpu.dtb.data_misses 44486 # DTB misses
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.read_accesses 911401 # DTB read accesses
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system.cpu.dtb.read_acv 582 # DTB read access violations
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system.cpu.dtb.read_hits 10188595 # DTB read hits
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system.cpu.dtb.read_misses 36193 # DTB read misses
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system.cpu.dtb.write_accesses 321574 # DTB write accesses
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system.cpu.dtb.write_acv 241 # DTB write access violations
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system.cpu.dtb.write_hits 6597047 # DTB write hits
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system.cpu.dtb.write_misses 8293 # DTB write misses
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system.cpu.fetch.Branches 14563531 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 8983923 # Number of cache lines fetched
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system.cpu.fetch.Cycles 23375540 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 455206 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 74277236 # Number of instructions fetch has processed
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system.cpu.fetch.MiscStallCycles 2199 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.SquashCycles 956999 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.106371 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 8983923 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 7807774 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 0.542514 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 102147731 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 0.727155 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.025450 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 87794438 85.95% 85.95% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 1023092 1.00% 86.95% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 1967534 1.93% 88.88% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 960313 0.94% 89.82% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 2993138 2.93% 92.75% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 661201 0.65% 93.39% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 802863 0.79% 94.18% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 1218814 1.19% 95.37% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 4726338 4.63% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 102147731 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.icache.ReadReq_accesses::0 8983923 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 8983923 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_avg_miss_latency::0 14917.128866 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11909.331981 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_hits::0 7937479 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 7937479 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_miss_latency 15609939999 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_rate::0 0.116480 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_misses::0 1046444 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1046444 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_mshr_hits 50514 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 11860861000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110857 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_misses 995930 # number of ReadReq MSHR misses
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 10883.333333 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_refs 7.971412 # Average number of references to valid blocks.
|
|
system.cpu.icache.blocked::no_mshrs 60 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_mshrs 653000 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.demand_accesses::0 8983923 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 8983923 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_avg_miss_latency::0 14917.128866 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 11909.331981 # average overall mshr miss latency
|
|
system.cpu.icache.demand_hits::0 7937479 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 7937479 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_miss_latency 15609939999 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_rate::0 0.116480 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.cpu.icache.demand_misses::0 1046444 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1046444 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_mshr_hits 50514 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_miss_latency 11860861000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_rate::0 0.110857 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_misses 995930 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.occ_%::0 0.995671 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_blocks::0 509.783438 # Average occupied blocks per context
|
|
system.cpu.icache.overall_accesses::0 8983923 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 8983923 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_avg_miss_latency::0 14917.128866 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 11909.331981 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_hits::0 7937479 # number of overall hits
|
|
system.cpu.icache.overall_hits::1 0 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 7937479 # number of overall hits
|
|
system.cpu.icache.overall_miss_latency 15609939999 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_rate::0 0.116480 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.cpu.icache.overall_misses::0 1046444 # number of overall misses
|
|
system.cpu.icache.overall_misses::1 0 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1046444 # number of overall misses
|
|
system.cpu.icache.overall_mshr_hits 50514 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_miss_latency 11860861000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_rate::0 0.110857 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_misses 995930 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.replacements 995232 # number of replacements
|
|
system.cpu.icache.sampled_refs 995743 # Sample count of references to valid blocks.
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.tagsinuse 509.783438 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 7937478 # Total number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 25287643000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
|
system.cpu.idleCycles 34765240 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.iew.EXEC:branches 9170733 # Number of branches executed
|
|
system.cpu.iew.EXEC:nop 3662671 # number of nop insts executed
|
|
system.cpu.iew.EXEC:rate 0.420879 # Inst execution rate
|
|
system.cpu.iew.EXEC:refs 17068903 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:stores 6620272 # Number of stores executed
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu.iew.WB:consumers 34614422 # num instructions consuming a value
|
|
system.cpu.iew.WB:count 57031603 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:fanout 0.763117 # average fanout of values written-back
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:producers 26414846 # num instructions producing a value
|
|
system.cpu.iew.WB:rate 0.416554 # insts written-back per cycle
|
|
system.cpu.iew.WB:sent 57130351 # cumulative count of insts sent to commit
|
|
system.cpu.iew.branchMispredicts 839771 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewBlockCycles 9768928 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewDispLoadInsts 11058875 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1801420 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewDispSquashedInsts 1004974 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispStoreInsts 7015626 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispatchedInsts 65914650 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts 10448631 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 528111 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 57623776 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 52093 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 6603 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 1639247 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 554420 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 311339 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 434411 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 10284 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 46318 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 18429 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 1751469 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 624045 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 46318 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 408059 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 431712 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 0.387716 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.387716 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7287 0.01% 0.01% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 39633385 68.15% 68.17% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 62109 0.11% 68.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25611 0.04% 68.32% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.32% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.32% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.32% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3637 0.01% 68.32% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 10799740 18.57% 86.90% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 6666948 11.46% 98.36% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 953172 1.64% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::total 58151889 # Type of FU issued
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 434913 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.007479 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 52889 12.16% 12.16% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 12.16% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.16% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.16% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.16% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.16% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.16% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.16% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.16% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 280249 64.44% 76.60% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 101775 23.40% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 102147731 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.569292 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.137713 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0 73060847 71.52% 71.52% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1 14641510 14.33% 85.86% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2 6377407 6.24% 92.10% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3 3918998 3.84% 95.94% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4 2506307 2.45% 98.39% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5 1046173 1.02% 99.42% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6 456673 0.45% 99.86% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7 116088 0.11% 99.98% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 23728 0.02% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 102147731 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:rate 0.424736 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 60199205 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 58151889 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 2052774 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 8775393 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 35779 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1385007 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 4703772 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.fetch_accesses 1302209 # ITB accesses
|
|
system.cpu.itb.fetch_acv 948 # ITB acv
|
|
system.cpu.itb.fetch_hits 1264828 # ITB hits
|
|
system.cpu.itb.fetch_misses 37381 # ITB misses
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed
|
|
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal::swpipl 175662 91.19% 93.39% # number of callpals executed
|
|
system.cpu.kern.callpal::rdps 6793 3.53% 96.92% # number of callpals executed
|
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
|
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
|
|
system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
|
|
system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
|
|
system.cpu.kern.callpal::rti 5220 2.71% 99.64% # number of callpals executed
|
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu.kern.callpal::total 192631 # number of callpals executed
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.hwrei 211789 # number of hwrei instructions executed
|
|
system.cpu.kern.inst.quiesce 6384 # number of quiesce instructions executed
|
|
system.cpu.kern.ipl_count::0 74950 40.95% 40.95% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::21 237 0.13% 41.08% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::22 1889 1.03% 42.12% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::31 105933 57.88% 100.00% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::total 183009 # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_good::0 73583 49.29% 49.29% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::22 1889 1.27% 50.71% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::31 73583 49.29% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::total 149292 # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_ticks::0 1824774879500 97.72% 97.72% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::21 102464000 0.01% 97.73% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::22 392165500 0.02% 97.75% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::31 42089912000 2.25% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::total 1867359421000 # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_used::0 0.981761 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::31 0.694618 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.mode_good::kernel 1911
|
|
system.cpu.kern.mode_good::user 1741
|
|
system.cpu.kern.mode_good::idle 170
|
|
system.cpu.kern.mode_switch::kernel 5971 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::user 1741 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches
|
|
system.cpu.kern.mode_switch_good::kernel 0.320047 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::total 1.401192 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_ticks::kernel 31307096500 1.68% 1.68% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::user 3189085000 0.17% 1.85% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::idle 1832863231500 98.15% 100.00% # number of ticks spent at the given mode
|
|
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
|
|
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
|
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
|
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
|
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
|
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
|
system.cpu.memDep0.conflictingLoads 3116609 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 2798105 # Number of conflicting stores.
|
|
system.cpu.memDep0.insertedLoads 11058875 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 7015626 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.numCycles 136912971 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 14296513 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 38253474 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 1101619 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 39527204 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 2223744 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:ROBFullEvents 15702 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.RENAME:RenameLookups 83467187 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 68675679 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 46041377 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 12627654 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 1639247 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 5214289 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 7787901 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 28842822 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 1704528 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 12805525 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 256634 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 1324969 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::1 115277.445087 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency 63277.445087 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_miss_latency 19942998 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_misses::1 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_mshr_miss_latency 10946998 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::1 137793.747738 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency 85790.377840 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_miss_latency 5725605806 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
|
system.iocache.WriteReq_mshr_miss_latency 3564761780 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
|
|
system.iocache.avg_blocked_cycles::no_mshrs 6164.456543 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.blocked::no_mshrs 10470 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_mshrs 64541860 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
|
|
system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::1 137700.390749 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency 85697.034823 # average overall mshr miss latency
|
|
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
|
|
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
|
|
system.iocache.demand_miss_latency 5745548804 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::1 41725 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.iocache.demand_mshr_miss_latency 3575708778 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.occ_%::1 0.079211 # Average percentage of cache occupancy
|
|
system.iocache.occ_blocks::1 1.267376 # Average occupied blocks per context
|
|
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
|
|
system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::1 137700.390749 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency 85697.034823 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.iocache.overall_hits::0 0 # number of overall hits
|
|
system.iocache.overall_hits::1 0 # number of overall hits
|
|
system.iocache.overall_hits::total 0 # number of overall hits
|
|
system.iocache.overall_miss_latency 5745548804 # number of overall miss cycles
|
|
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.iocache.overall_misses::0 0 # number of overall misses
|
|
system.iocache.overall_misses::1 41725 # number of overall misses
|
|
system.iocache.overall_misses::total 41725 # number of overall misses
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.iocache.overall_mshr_miss_latency 3575708778 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.iocache.replacements 41685 # number of replacements
|
|
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.iocache.tagsinuse 1.267376 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.warmup_cycle 1716180121000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.writebacks 41512 # number of writebacks
|
|
system.l2c.ReadExReq_accesses::0 300511 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 300511 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_avg_miss_latency::0 52374.719501 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40217.943752 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_miss_latency 15739179332 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_misses::0 300511 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 300511 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_mshr_miss_latency 12085934495 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_misses 300511 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadReq_accesses::0 2097129 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 2097129 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_avg_miss_latency::0 52047.601080 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 40016.046370 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_hits::0 1785718 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1785718 # number of ReadReq hits
|
|
system.l2c.ReadReq_miss_latency 16208195500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_rate::0 0.148494 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_misses::0 311411 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 311411 # number of ReadReq misses
|
|
system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_miss_latency 12461397000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::0 0.148493 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_misses 311410 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable_latency 810521500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.SCUpgradeReq_accesses::0 29987 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 29987 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::0 52320.338813 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::1 inf # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40001.217194 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_miss_latency 1568930000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_misses::0 29987 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 29987 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency 1199516500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_misses 29987 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_accesses::0 100109 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 100109 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_avg_miss_latency::0 52260.720754 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 40126.157488 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_miss_latency 5231768494 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_misses::0 100109 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 100109 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency 4016989500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_misses 100109 # number of UpgradeReq MSHR misses
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_mshr_uncacheable_latency 1116126498 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.Writeback_accesses::0 430200 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 430200 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_hits::0 430200 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 430200 # number of Writeback hits
|
|
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_refs 4.595902 # Average number of references to valid blocks.
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.demand_accesses::0 2397640 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2397640 # number of demand (read+write) accesses
|
|
system.l2c.demand_avg_miss_latency::0 52208.246855 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency 40115.197052 # average overall mshr miss latency
|
|
system.l2c.demand_hits::0 1785718 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1785718 # number of demand (read+write) hits
|
|
system.l2c.demand_miss_latency 31947374832 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_rate::0 0.255218 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.l2c.demand_misses::0 611922 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 611922 # number of demand (read+write) misses
|
|
system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_miss_latency 24547331495 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_rate::0 0.255218 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_misses 611921 # number of demand (read+write) MSHR misses
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.occ_%::0 0.090196 # Average percentage of cache occupancy
|
|
system.l2c.occ_%::1 0.378860 # Average percentage of cache occupancy
|
|
system.l2c.occ_blocks::0 5911.076462 # Average occupied blocks per context
|
|
system.l2c.occ_blocks::1 24828.993432 # Average occupied blocks per context
|
|
system.l2c.overall_accesses::0 2397640 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2397640 # number of overall (read+write) accesses
|
|
system.l2c.overall_avg_miss_latency::0 52208.246855 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency 40115.197052 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_hits::0 1785718 # number of overall hits
|
|
system.l2c.overall_hits::1 0 # number of overall hits
|
|
system.l2c.overall_hits::total 1785718 # number of overall hits
|
|
system.l2c.overall_miss_latency 31947374832 # number of overall miss cycles
|
|
system.l2c.overall_miss_rate::0 0.255218 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.l2c.overall_misses::0 611922 # number of overall misses
|
|
system.l2c.overall_misses::1 0 # number of overall misses
|
|
system.l2c.overall_misses::total 611922 # number of overall misses
|
|
system.l2c.overall_mshr_hits 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_miss_latency 24547331495 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_rate::0 0.255218 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_misses 611921 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_uncacheable_latency 1926647998 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.l2c.replacements 396067 # number of replacements
|
|
system.l2c.sampled_refs 427735 # Sample count of references to valid blocks.
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.l2c.tagsinuse 30740.069893 # Cycle average of tags in use
|
|
system.l2c.total_refs 1965828 # Total number of references to valid blocks.
|
|
system.l2c.warmup_cycle 5645113000 # Cycle when the warmup percentage was hit.
|
|
system.l2c.writebacks 119080 # number of writebacks
|
|
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
|
|
---------- End Simulation Statistics ----------
|