ade53def92
This patch moves the connection of the system port to create_system in Ruby.py. Thereby it allows the failing Ruby test (and other Ruby systems) to run again.
116 lines
3.7 KiB
Python
116 lines
3.7 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
|
# Copyright (c) 2009 Advanced Micro Devices, Inc.
|
|
# All rights reserved.
|
|
#
|
|
# Redistribution and use in source and binary forms, with or without
|
|
# modification, are permitted provided that the following conditions are
|
|
# met: redistributions of source code must retain the above copyright
|
|
# notice, this list of conditions and the following disclaimer;
|
|
# redistributions in binary form must reproduce the above copyright
|
|
# notice, this list of conditions and the following disclaimer in the
|
|
# documentation and/or other materials provided with the distribution;
|
|
# neither the name of the copyright holders nor the names of its
|
|
# contributors may be used to endorse or promote products derived from
|
|
# this software without specific prior written permission.
|
|
#
|
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
#
|
|
# Authors: Ron Dreslinski
|
|
# Brad Beckmann
|
|
|
|
import m5
|
|
from m5.objects import *
|
|
from m5.defines import buildEnv
|
|
from m5.util import addToPath
|
|
import os, optparse, sys
|
|
|
|
if buildEnv['FULL_SYSTEM']:
|
|
panic("This script requires system-emulation mode (*_SE).")
|
|
|
|
# Get paths we might need. It's expected this file is in m5/configs/example.
|
|
config_path = os.path.dirname(os.path.abspath(__file__))
|
|
config_root = os.path.dirname(config_path)
|
|
m5_root = os.path.dirname(config_root)
|
|
addToPath(config_root+'/configs/common')
|
|
addToPath(config_root+'/configs/ruby')
|
|
|
|
import Ruby
|
|
|
|
parser = optparse.OptionParser()
|
|
|
|
#
|
|
# Add the ruby specific and protocol specific options
|
|
#
|
|
Ruby.define_options(parser)
|
|
|
|
execfile(os.path.join(config_root, "configs/common", "Options.py"))
|
|
|
|
(options, args) = parser.parse_args()
|
|
|
|
#
|
|
# Set the default cache size and associativity to be very small to encourage
|
|
# races between requests and writebacks.
|
|
#
|
|
options.l1d_size="256B"
|
|
options.l1i_size="256B"
|
|
options.l2_size="512B"
|
|
options.l3_size="1kB"
|
|
options.l1d_assoc=2
|
|
options.l1i_assoc=2
|
|
options.l2_assoc=2
|
|
options.l3_assoc=2
|
|
|
|
#
|
|
# create the tester and system, including ruby
|
|
#
|
|
tester = RubyTester(checks_to_complete = 100, wakeup_frequency = 10)
|
|
|
|
system = System(tester = tester, physmem = PhysicalMemory())
|
|
|
|
Ruby.create_system(options, system)
|
|
|
|
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
|
|
|
|
#
|
|
# The tester is most effective when randomization is turned on and
|
|
# artifical delay is randomly inserted on messages
|
|
#
|
|
system.ruby.randomization = True
|
|
|
|
for ruby_port in system.ruby._cpu_ruby_ports:
|
|
#
|
|
# Tie the ruby tester ports to the ruby cpu ports
|
|
#
|
|
tester.cpuPort = ruby_port.port
|
|
|
|
#
|
|
# Tell the sequencer this is the ruby tester so that it
|
|
# copies the subblock back to the checker
|
|
#
|
|
ruby_port.using_ruby_tester = True
|
|
|
|
#
|
|
# Ruby doesn't need the backing image of memory when running with
|
|
# the tester.
|
|
#
|
|
ruby_port.access_phys_mem = False
|
|
|
|
# -----------------------
|
|
# run simulation
|
|
# -----------------------
|
|
|
|
root = Root( system = system )
|
|
root.system.mem_mode = 'timing'
|
|
|
|
# Not much point in this being higher than the L1 latency
|
|
m5.ticks.setGlobalFrequency('1ns')
|